Dedicated Circuitry in Stratix GX Devices Eases Design of High-Speed Systems
San Jose, Calif., November 6, 2002--With the unveiling of its new Stratix™ GX device family, Altera Corporation (NASDAQ: ALTR) has introduced the FPGA industry's first hard silicon solution for embedded dynamic phase alignment (DPA), the company announced today. The high performance offered by DPA makes it a key complement to the Stratix GX device family's 3.125-Gbps transceiver blocks.
The importance of phase alignment has grown as source-synchronous interface protocols reach data rates close to 1 Gbps. At these rates, the slightest mismatch between clocks and their associated data signals due to board-level phenomena like skew and jitter can result in data transfer errors. DPA reduces the impact of these effects by repeatedly comparing incoming data with the system clock and continuously aligning the clock to match the data bits. Many interface standards organizations have incorporated DPA recommendations and requirements into their interfaces, including the Optical Internetworking Forum (OIF) with the System Packet Interface Level 4 (SPI-4) Phase 2 standard.
"The depth and breadth of Altera's overall product strategy in providing ASIC design alternatives is demonstrated by their Stratix GX device family announcement. The development and introduction of Altera's Mercury™ device family allowed them to explore 'real-world' high-speed interface issues and provided the experience needed to generate a robust collection of product support material that goes well beyond a device family data sheet," said analyst Cary Snyder of PC2 Consulting. "The Stratix GX transceivers being complemented by incorporation of hard DPA logic into each source-synchronous channel, unlike other methods to perform this function, illustrates Altera's solid understanding and acceptance of what it takes to build highly reliable and fault-tolerant systems."
Stratix GX devices achieve balanced data transfer with source-synchronous I/O channels capable of 1-Gbps performance. These channels, located on the opposite side of the device from the Stratix GX transceiver blocks, enable users to move data on and off the chip at complementary rates using LVDS, PCML, or LVPECL I/O standards across multiple channels. Each channel is equipped with dedicated serializer/deserializer (SERDES) and DPA circuitry.
By relying on dedicated circuitry, the implementation of DPA in Stratix GX FPGAs offers several advantages over other programmable logic-based DPA offerings, including lower power usage, better immunity to temperature and voltage variation, conservation of clock management resources, higher operational frequencies, and zero consumption of valuable logic resources in the device.
"DPA in Stratix GX devices continues Altera's tradition of leading the industry in offering innovative device features to support advanced high-speed I/O interfaces," said David Greenfield, senior director of FPGA marketing at Altera. "In 1999, Altera introduced the industry's first dedicated circuitry for high-speed, differential I/O signals in the APEX™ 20KE device family. Subsequently, in 2001, Altera shipped Mercury devices, the industry's first PLDs to include clock-data recovery. By including DPA in Stratix GX devices, Altera gives customers the ability to meet stringent timing requirements and maintain protocol compliance without sacrificing time-to-market."
The DPA feature is available in all Stratix GX devices. Altera has published a white paper that further details the need for DPA in high-speed programmable logic, which can be accessed at www.altera.com/literature/lit-wp.html.
About Stratix GX Devices
The Stratix GX family is Altera's second-generation embedded transceiver family based on a 0.13-µm process technology with 1.5-V core voltage. Stratix GX devices have up to 20 embedded 3.125-Gbps transceivers and up to 45 source-synchronous channels with dedicated DPA circuitry capable of supporting up to 1-Gbps source-synchronous data transfers. Stratix GX devices also offer up to 41,250 logic elements, 3.27 Mbits of TriMatrix™ memory, 14 DSP blocks, eight phase locked loops (PLLs), Terminator™ technology for impedance matching and signal integrity, and advanced I/O buffers capable of interfacing with high-speed memory devices such as DDR SDRAM, QDR SRAM, QDRII SRAM, ZBT SRAM, DDR FCRAM, and SDR SRAM devices.
Altera Corporation (NASDAQ: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at www.altera.com.