Arasan Announces Industry's First MIPI C-PHY HDK
San Jose, CA -- Dec 5, 2017 -- Arasan Chip Systems, a leading provider of IP for semiconductor design and manufacturing, today announced availability of its MIPI C-PHY[SM] HDK built using an Arasan C-PHY ASIC. The HDK supports C-PHY v1.1 with speeds of up to 2.5 GHz and D-PHY v1.2 also with speeds of up to 2.5GHz. Arasan’s HDK offers the fastest and surest path for companies looking to adopt the latest MIPI standards. The HDK is part of Arasan’s Total IP Solution for MIPI.
The C-PHY HDK board will be assembled with either a C-PHY TSMC 28nm or TSMC 12nm ASIC.
This HDK enables customers to prototype their C-PHY based projects using Arasan’s MIPI DSI or CSI IP Cores and software stacks. The HDK can be easily integrated with Xilinx based FPGA platforms using a FMC Connector. After prototyping, the entire design can be licensed including the MIPI C- PHY / D-PHY combo IP GDS II, MIPI CSI or DSI Verilog RTL and firmware.
Arasan’s C-PHY IP has been adopted extensively by automobile, drone and imaging SoC manufacturers. Arasan is a TSMC OIP partner supporting physical interface IP for MIPI, JEDEC, ONFI, USB and SD. The C-PHY HDK board will be assembled with either a C-PHY TSMC 28nm or TSMC 12nm ASIC.
Availability
Arasan CPHY HDK is available for immediate sale. Due to high demand, the lead time for delivery is 4-6 weeks from order date with a minimum order quantity of 12 boards.
|
Arasan Chip Systems Hot IP
Related News
- Arasan's MIPI CSI-2 IP achieves ISO26262 ASIL-C Certification for MIPI C-PHY Connectivity
- Arasan Announces it's 2'nd Generation MIPI C-PHY / D-PHY IP Combo Core for C-PHY v1.2 Specifications
- Arasan and Test Evolution announce Industry's first C-PHY / D-PHY Combo Compliance Analyzer with Arasan's Total MIPI IP Solution
- Arasan announces MIPI CSI IP for FPGA supporting full C-PHY 2.0 speeds
- Arasan announces its next generation of C-PHY/ D-PHY Combo IP Core compliant with the latest MIPI Specifications
Breaking News
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- T2M-IP Unveils Revolutionary MIPI D-PHY & DSI Controller IP Cores with speed 2.5Gbps/lane, Redefining High-Speed Data Transfer and Display Interfaces
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Faraday Partners with Arm to Innovate AI-driven Vehicle ASICs
- Semiconductor Capacity Is Up, But Mind the Talent Gap
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
E-mail This Article | Printer-Friendly Page |