Helic Tools Integrated into Synopsys Custom Design Platform to Accelerate Robust Design
MOUNTAIN VIEW, Calif. and SANTA CLARA, Calif. -- Dec. 14, 2017 -- Synopsys, Inc. (Nasdaq: SNPS) and Helic, Inc. today announced that the companies have collaborated to integrate Helic's VeloceRF™ RF device synthesis, RaptorX™ EM modeling and Exalto® EM parasitic extraction and signoff tools with Synopsys' Custom Design Platform. The result of the collaboration is a complete solution for electromagnetic-aware (EM-aware) layout and analysis of mixed-signal, analog, and RF designs.
"At Asahi Kasei Microdevices Corporation (AKM) our custom design flow is based on Synopsys' Custom Compiler tool and we use Helic's RF circuit design and verification solution," said Koji Tomioka, General Manager of AKM. "We believe this unified EM-aware flow will help our engineers accelerate their pace of innovation and increase the robustness of their designs."
The Synopsys/Helic EM-aware flow provides a GUI within Custom Compiler™ for users to generate DRC-clean layouts of single- or multi-inductor spiral structures with VeloceRF. VeloceRF also creates schematic symbols and simulation models that are ready for use in Custom Compiler, and LVS rules for verification of the generated devices with IC Validator. The flow also includes a tight integration of Helic's RaptorX, for in-design analysis of EM effects during layout. Early awareness of EM effects helps reduce iterations during signoff verification. The Exalto EM parasitic extraction engine works with Synopsys' StarRC™ tool to provide a complete RLCK parasitic netlist that is ready for RF simulation. Synopsys Custom Design Platform users can perform frequency-domain simulation of their circuits with HSPICE® technology and analyze the results with the Custom WaveView™ solution.
"Designers of chips operating at high data bandwidth and frequencies need detailed parasitic extraction and EM-aware analysis early and throughout the physical design flow," said Yorgos Koutsoyannopoulos, CEO of Helic. "Bringing our EM-aware modeling, analysis, and signoff technology into the Synopsys Custom Compiler environment will enable our mutual customers to avoid excessive margining and guardbanding and reduce the risk of silicon surprises."
"As the Custom Compiler user community continues to grow, we are aggressively expanding our third-party ecosystem to support it," said Bijan Kiani, vice president of product marketing at Synopsys. "With this latest collaboration, we have worked closely with Helic to deliver a strong solution for EM-aware custom design to our mutual customers."
Helic and Synopsys tools comprising the integrated custom design solution are available now from their respective companies.
About the Synopsys Custom Design Platform
The Synopsys Custom Design Platform is a unified suite of design and verification tools that accelerates the development of robust custom designs. Anchored by the Custom Compiler custom design tool, the platform features industry-leading circuit simulation performance and a fast, easy-to-use custom layout editor. It includes technologies for parasitic extraction, reliability analysis, and physical verification. Key capabilities of the platform include physically-aware design, visually-assisted layout, and reliability-aware verification and IC Compiler™ II Custom Co-Design.
Physically-aware design minimizes the mismatch between pre- and post-layout simulation by fusing technologies from StarRC parasitic extraction into simulation and layout. Visually-assisted layout provides automation without requiring complicated constraints. Reliability-aware verification ensures robust design with signoff-accurate transistor-level EM/IR analysis, large-scale Monte Carlo simulation, aging analysis, and other verification checks. IC Compiler II Custom Co-design connects Synopsys' digital and analog tools into a solution for mixed-signal system-on-chip (SoC) implementation.
The Synopsys Custom Design Platform is based on the OpenAccess database, includes open APIs for third-party tool integration, and supports programming in TCL and Python®. The platform includes HSPICE and FineSim® SPICE, CustomSim™ FastSPICE, Custom Compiler layout and schematic editor, StarRC parasitic extraction, and IC Validator physical verification tools. For more information, visit www.customcompiler.info.
Helic of Santa Clara, Calif., develops and markets Electronic Design Automation (EDA) software that mitigates the risk of crosstalk in high-speed System on Chip (SoC) Designs and Analog/RF designs. Since 2000, its cutting-edge technology enables analog/RF and high-frequency IC design engineers to synthesize inductive devices and model electromagnetic and parasitic phenomena with accuracy, speed and seamless design flow interoperability. In the last few years, as frequency and bandwidth rise, Helic tools are used by SoC design teams from many of the top-10 semiconductor companies to analyze crosstalk in applications such as wireless communications, Internet of Things (IoT), computing, automotive and high-speed networking. Visit www.helic.com for more information.
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.