SoC-e releases IEC 61850/62351 SASCrypt IP Core
February 7, 2018 -- IEC 62351 is a standard developed for handling the security of IEC 61850 series protocols amongs others. The different security objectives include authentication of data transfer through digital signatures, ensuring only authenticated access, prevention of eavesdropping, prevention of playback and spoofing, and intrusion detection. The IEC 62351-6 part provides security for IEC 61850 profiles.
SoC-e has released the IEC 61850/62351 Substation Automation Systems Cryptographic (SASCrypt) IP Core. This IP Core secures the strict real-time traffic used in the Substation Automation Systems and in new Smart Grid premises. It protects GOOSE and Sample-Measured-Values (SMV) frames used to communicate critical equipment within these premises like Merging Units or IEDs. This low-latency IP Core is capable of encrypting, decrypting and authenticating GOOSE or SMV at wire-speed.
SASCrypt IP Core integrates a proprietary low-latency cryptographic cipher specifically optimized for this task. This cipher module provides the required performance with an optimum resource utilization and introducing a delay of few microseconds.
SASCrypt IP is supported on the following Xilinx FPGA Families:
- 6-Series (Spartan, Virtex)
- 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
- Ultrascale (Kintex, Virtex)
- Ultrascale+ (Zynq MPSoC, Kintex, Virtex)
The reference designs that include the SASCrypt IP Core can be evaluated in SoC-e’s SMARTzynq Brick and SMARTmpsoc Brick.
|
Related News
- SoC-e releases Multiport Time Sensitive Networking (TSN) IP Core
- SoC-e networking IP porfolio extends with SpaceWire: The standard for Spacecraft communication networks
- GE Power Management licenses SoC-e wire-speed Cryptography IP for GOOSE&Sampled Values Security
- Stage Tec introduces HSR for Professional Audio Broadcasting using SoC-e Technology
- SoC-e's 1588Tiny IP Core now supports Layer-3 PTP operation
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |