Interview with Rick O'Connor of RISC-V Foundation

March 08, 2018 // By Peter Clarke, eeNews

The RISC-V Foundation was present at the Embedded World exhibition with its own booth that also hosted a number of companies within its growing ecosystem. eeNews caught up with Rick O'Connor, executive director of the foundation and asked why a new and open processor architecture was relevant to embedded applications.

RISC-V Processor - RV12 - 32/64 bit, Single Core CPU Compact Implementation of the RISC-V RV32IMC ISA

"RISC-V (pronounced five) was really the result of a summer academic program to create a processor that could be used to teach processor design in 2010," O'Connor explained. The obvious choices for teaching had been the x86 and ARM but their instruction sets had become complicated and there were IP and license issues so using them for teaching was not really possible. The the primary motivation was for something simple but that used the best ideas for academia. It took until 2013 to develop and May 2014 was when the specification was first frozen.

But the reason that RISC-V Foundation was formed to look after the ISA specification was because companies liked the open-ness and wanted to make use of the architecture in the commercial environment, O'Connor added. "There are now more than 100 companies in the RISC-V Foundation. We call it an open instruction set architecture rather than open-source hardware. It's not the first. SPARC is open and there have been others."

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