PLDA Announces New Test And Validation Platforms For PCIe
PLDA has leveraged their extensive PCIe expertise to provide a comprehensive suite of Test and Validation solutions for the PCI Express protocol, enabling faster and more affordable validation of PCIe silicon and devices
SAN JOSE, Calif., April 23, 2018 – PLDA®, the industry leader in PCI Express® interface IP solutions today announced the launch of a new Test and Validation Platform line of products, aimed at creating easier and faster routes to PCIe® 4.0 design. It includes their Inspector ME, Gen4SWITCH, Gen4ENDPOINT and VU3P-IPP products, which offer a range of options to test and validate designs in Switch, Root Port or Endpoint configuration at PCIe 4.0 16GT/s speeds. These innovative products allow PCIe designers to more easily validate their designs, reducing their time-to-market.
In addition to their core business of licensing PCIe semiconductor IP, PLDA has a long history of robust hardware designs. PLDA initially built its first PCIe 4.0 platform, Gen4SWITCH, as a way to demonstrate the PCIe 4.0 technology and to test designs at PCIe 4.0 speed for its own needs. Widely used during tradeshows and at PCI-SIG workshops as an early PCIe 4.0 host platform, Gen4SWITCH has become a star product in high demand, and has spawned a complete Test and Validation product line, targeted specifically at the needs of PCIe 4.0 SoC designers and system vendors.
OVERVIEW OF THE PCIe 4.0 PLATFORMS:
PLDA’s Diagnostic and Debug Platforms
- PLDA Inspector ME: Interposer module for in-system PCIe link diagnostic and add-in card testing at up to PCIe 4.0 16GT/s speed.
Validation Platforms
- PLDA Gen4ENDPOINT: PCIe 4.0 endpoint adapter card that enables the testing of PCIe 4.0 Host adapters and motherboards, Root Port silicon and PHY test chips
- PLDA Gen4SWITCH: PCIe 4.0 switch adapter card with 1 downstream port that enables the testing of PCIe 4.0 Endpoint adapters and PHY test chips
IP Prototyping Platforms
- VU3P-IPP: FPGA prototyping card based on Virtex® Ultrascale+ VU3P for PCIe (upstream and downstream) and FireFly™ prototyping.
“Using PLDA’s Inspector for PCIe 4.0 host system with Gen4ENDPOINT allowed us to quickly demonstrate the capabilities of our Xgig® 4K16 PCIe 4.0 Protocol Analyzer/Jammer with real PCIe traffic at 16GT/sec” said Tom Fawcett, VP and GM, Lab and Production Business Unit at VIAVI Solutions. “The Xgig 4K16 product family, which includes CEM and other interposers for PCIe system attachment, provides dynamic trace capture and triggering for in-depth LTSSM, ASPM, NVMe and other analyses, enabling quick IC, FPGA, system or application debug. We’re glad to see PLDA leveraging their PCIe semiconductor IP expertise to supply high quality host and end-point devices for the new PCI Express 4.0 standard."
According to Arnaud Schleich, CEO of PLDA “We were initially surprised at the interest PCIe designers had in our platforms during the PCI-SIG Workshops and DevCon events and realized that there was a true need for innovative Test and Validation products for PCIe 4.0 designs.” Schleich added “We are pleased to provide SoC designers and system vendors with a new category of test and validation products at PCIe 4.0 speeds as they design their next generation products.”
More Information:
If you want a real demonstration, you can visit PLDA’s booth at :
- TSMC Symposium SANTA CLARA (Booth ) (May 1st)
- PCI-SIG DevCon Munchen 2018 (Booth 2) (May 7-8)
- TSMC SYMPOSIUM Shanghaï (May 22)
About PLDA
PLDA has been successfully delivering PCI and PCI Express IP for more than 20 years. With over 6,200 licenses, PLDA has established a vast customer base and the world’s broadest PCIe ecosystem. PLDA has maintained its leadership over four generations of PCI Express specifications, enabling customers to reduce risk and accelerate time to market for their ASIC and FPGA based designs. PLDA provides a complete PCIe solution with its IP cores, FPGA boards for ASIC prototyping, PCIe BFM/testbenches, PCIe drivers, and APIs. PLDA is a global company with offices in North America (San Jose, California), Europe (France, Italy, and Bulgaria), and Asia (China, Taiwan).
|
Related News
- PLDA Announces "Inspector" - An Evolution of the PCI Express 4.0 PDK That Enables PCIe 4.0 Technology Design Validation and Performance Optimization Today
- GUC PCIe 3 PHY IP & PLDA EP Controller Combo Passes Compliance Test
- Synopsys Demonstrates Industry's First Interoperability of PCI Express 6.0 IP with Intel's PCIe 6.0 Test Chip
- Imperas announces RISC-V Physical Memory Protection (PMP) Architectural Validation test suite for high quality security applications
- Avery Design Partners with S2C to Bring PCIe 6.0 and LPDDR5 and HBM3 Speed Adapters to FPGA prototyping solutions for Data Center and AI/ML SoC Validation
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |