Low power consumption and lowest jitter increase reliability, reduce cost
PALO ALTO, Calif., Nov. 20, 2002 - Agilent Technologies Inc. (NYSE: A) today announced a breakthrough with its new 0.13 micron embedded serializer/deserailizer (SerDes) intellectual property (IP) semiconductor core. The new IP core offers low power consumption and the lowest possible jitter available, enabling Agilent to integrate as many as 150 SerDes channels onto a single application specific integrated circuit (ASIC), each operating at up to 3.125 Gb/s.
The breakthrough IP core enables the integration of more SerDes channels onto a single chip than previously possible. The integration of multiple channels also will allow network equipment manufacturers (NEMs) increased reliability and reduced size, complexity and cost of SerDes system designs, used to enable next-generation high bandwidth networking and storage systems.
"Agilent has staked out a position as the technology leader in embedded SerDes," said James Stewart, vice president and general manager of Agilent's ASIC Products Division. "This announcement extends our leadership in this area, and we look forward to passing this technology breakthrough onto our customers by delivering complex, high-performance chips on time and in volume."
Agilent's ASIC capability is based on a heritage of high transistor ASIC designs with extremely high SerDes channel count. Previously, Agilent integrated more than 50 2.5 Gb/s transmit and receive channels on a single CMOS (complimentary metal oxide semiconductor) chip and subsquently produced an ASIC with 36 multi-rate SerDes Channels operating at up to 3.125 GB/s.
Agilent's new embedded SerDes core exhibits the industry's lowest jitter performance. The jitter performance specification is a critical measure of how well network elements operate -- the lower the jitter, the better. Any phase variations or jitter induced in the network can cause a degradation of transmission quality, bit errors, and data loss. At less than 2 picoseconds root mean square (RMS), the new Agilent SerDes core provides random jitter performance that will support bit error rates (BER) of better than 10-17 for network equipment backplane applications. BER indicates how often a bit will be misinterpreted, and lower BER results in more reliable and consistent data transmission.
Agilent offers the new 0.13 micron SerDes core in pairs, triplets, or octets that can be combined in a very high channel-count chip. The low power core features 75mW typical operation and is XAUI, Fibre Channel, and InfiniBand compliant. It also features a selectable reference clock, and supports both backplane and chip-to-chip applications. The maximum usable runlength (defined as a string of consecutive 1's or 0's) is in excess of 100 bits, which exceeds SONET/SDH requirements.
With more than two decades of ASIC design and manufacturing experience, Agilent offers state-of-the-art hierarchical design methodology and design-for-test capability. The company has an outstanding track record of first-pass success in the design and manufacture of these chips. These strengths, combined with an extensive IP portfolio, facilitate rapid integration of quality, high-performance ASICs for applications including communications, imaging and computing. More information is available at www.agilent.com/semiconductors.
About Agilent Technologies
Agilent Technologies Inc. (NYSE: A) is a global technology leader in communications, electronics and life sciences. The company's 36,000 employees serve customers in more than 120 countries. Agilent had net revenue of $6 billion in fiscal year 2002. Information about Agilent is available on the Web at www.agilent.com.