Dolphin Integration introduces new Dual Port memory compilers in TSMC 40 nm
Grenoble, France – May 21, 2018 -- Dolphin Integration, leader in innovative design solutions for the next generation of energy-efficient System-on-Chips, has announced the launch of its new Dual Port RAM compiler ”ERA” in TSMC 40 nm. This cost-effective RAM compiler creates memories maximizing battery life whilst reducing silicon area. Capable of generating instances ranging from 64 bits to 288 kbits, it also features a new ultra-low leakage stand-by “NAP” mode, allowing a leakage reduction of up to 35% compared to standard stand-by modes with a single clock cycle wake-up time. WIPE, a new feature available as an add-on, allows the reset of the memory in only 5 clock cycles.
The ERA Dual-Port memory compiler is available in Single or Dual Rail with high density, low power, low leakage optimization, in TSMC 40 nm uLP or uLPeF. Power switches can be embedded as an option.
The ERA memory compilers are available for evaluation on your private ”MyDolphin” portal.
The ERA architecture has already been silicon proven in TSMC 55 nm and migrated to the TSMC 40 nm technology node. The following views are available:
- Simulation (Verilog)
- layout (GDSII)
- footprint (LEF)
- timing/power (Liberty)
- MBIST (Tessent) models
About Dolphin Integration
Dolphin Integration is a pioneer in solutions allowing the design of energy efficient Systems-on-Chip, with a unique offering of high-density Foundation, Feature and SoC Fabric Silicon IP components best suited for low power-consumption. Dolphin Integration’s success stories range far and wide and include all the major actors in the semiconductor industry. With 30 years of experience in the integration of silicon IP components coupled with complementary EDA solutions for a power-integrity driven approach to design, and ASIC/SoC design and fabrication, Dolphin Integration is a true one-stop shop.
Not just one more supplier of Technology, but the provider of the Dolphin Integration know-how!
If you liked reading our announcement visit us www.dolpin-integration.com
|
Dolphin Design Hot IP
Related News
- Dolphin Integration augments the TSMC IP Ecosystem at 40 nm ULP eFlash with new TITAN Read Only Memory
- Dolphin Integration launches a 65 nm compiler for Dual Port Register Files reaching the highest density
- Dolphin Integration breakthrough innovation for TSMC 180 nm BCD Gen 2 process: Up to 30% savings in silicon area with the new SpRAM RHEA
- Audio Codec IP - 40 nm: Dolphin Integration passed TSMC IP9000 Level 4 qualification at Low Power process
- Dolphin Integration sRAM compiler completes TSMC IP9000 Level 1 qualification at 85 nm Ultra Low Power process
Breaking News
- After TSMC fab in Japan, advanced packaging facility is next
- A System On Module (SoM) developed by Electra IC: BitFlex-SPB-A7 FPGA SoM
- Weebit Nano to demo its ReRAM technology on GlobalFoundries' 22FDX® platform
- SoC Secure Boot Hardware Engine IP Core Now Available from CAST
- QuickLogic and Zero-Error Systems Partner to Deliver Radiation-Tolerant eFPGA IP for Commercial Space Applications
Most Popular
- Former Moortec executives create chip monitor startup
- PrimisAI Unveils Premium Version of RapidGPT, Redefining Hardware Engineering
- Arteris Expands Ncore Cache Coherent Interconnect IP To Accelerate Leading-Edge Electronics Designs
- Arm Announces New Automotive Technologies to Accelerate Development of AI-enabled Vehicles by up to Two Years
- Arm's Broadest Ever Automotive Enhanced IP Portfolio Designed for the Future of Computing in Vehicles
E-mail This Article | Printer-Friendly Page |