Dolphin Integration introduces new Dual Port memory compilers in TSMC 40 nm
Grenoble, France – May 21, 2018 -- Dolphin Integration, leader in innovative design solutions for the next generation of energy-efficient System-on-Chips, has announced the launch of its new Dual Port RAM compiler ”ERA” in TSMC 40 nm. This cost-effective RAM compiler creates memories maximizing battery life whilst reducing silicon area. Capable of generating instances ranging from 64 bits to 288 kbits, it also features a new ultra-low leakage stand-by “NAP” mode, allowing a leakage reduction of up to 35% compared to standard stand-by modes with a single clock cycle wake-up time. WIPE, a new feature available as an add-on, allows the reset of the memory in only 5 clock cycles.
The ERA Dual-Port memory compiler is available in Single or Dual Rail with high density, low power, low leakage optimization, in TSMC 40 nm uLP or uLPeF. Power switches can be embedded as an option.
The ERA memory compilers are available for evaluation on your private ”MyDolphin” portal.
The ERA architecture has already been silicon proven in TSMC 55 nm and migrated to the TSMC 40 nm technology node. The following views are available:
- Simulation (Verilog)
- layout (GDSII)
- footprint (LEF)
- timing/power (Liberty)
- MBIST (Tessent) models
About Dolphin Integration
Dolphin Integration is a pioneer in solutions allowing the design of energy efficient Systems-on-Chip, with a unique offering of high-density Foundation, Feature and SoC Fabric Silicon IP components best suited for low power-consumption. Dolphin Integration’s success stories range far and wide and include all the major actors in the semiconductor industry. With 30 years of experience in the integration of silicon IP components coupled with complementary EDA solutions for a power-integrity driven approach to design, and ASIC/SoC design and fabrication, Dolphin Integration is a true one-stop shop.
Not just one more supplier of Technology, but the provider of the Dolphin Integration know-how!
If you liked reading our announcement visit us www.dolpin-integration.com
|
Dolphin Design Hot IP
Retention Alternative Regulator, combines high efficiency in normal mode and ult ...
Low frequency XTAL oscillator optimized for low power
Capacitor-less 106 dB dynamic range ADC with low power mode and ultra low latenc ...
Always-on Voice Activity Detection interfacing with analog microphones.
Ultra-low power always-ready MCU sub-system architecture
Related News
- Dolphin Integration augments the TSMC IP Ecosystem at 40 nm ULP eFlash with new TITAN Read Only Memory
- Dolphin Integration launches a 65 nm compiler for Dual Port Register Files reaching the highest density
- Dolphin Integration breakthrough innovation for TSMC 180 nm BCD Gen 2 process: Up to 30% savings in silicon area with the new SpRAM RHEA
- Ultra-low power memory generators silicon proven at TSMC 55 nm uLP and uLP eFlash
- Audio Codec IP - 40 nm: Dolphin Integration passed TSMC IP9000 Level 4 qualification at Low Power process
Breaking News
- Alphawave IP and Verisilicon Expand Partnership with $54M Multi-Year Exclusive Subscription Reseller Agreement for China Market
- BrainChip Inc. and NaNose Medical Successfully Detect COVID-19 in Exhaled Breath with Fast High-Accuracy Results
- TSMC Ranks in Top-10 For Capacity in Three Wafer Size Categories
- Palma Ceia SemiDesign Announces Nicky Wilkinson as Director IC Engineering
- Rambus and AMD Extend Patent License Agreement
Most Popular
- TSMC Ranks in Top-10 For Capacity in Three Wafer Size Categories
- CEVA's MotionEngine Smart TV Software Comes to More Smart TV brands via LG webOS
- North American Semiconductor Equipment Industry Posts January 2021 Billings, Topping $3 Billion for First Time
- Andes Technology and Rambus Collaborate to offer Secure Solution for MCU and IoT Applications
- SiPearl and Open-Silicon Research Collaborate to Accelerate Custom Silicon for High Performance Computing (HPC) Applications
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |