Azanda Network Devices leverages Databahn memory controllers in its single-chip OC-48 Traffic Manager and ATM SAR
Palo Alto, Calif., December 2, 2002--- Denali Software, Inc., the leading provider of semiconductor intellectual property (SIP) and engineering design automation (EDA) tools for memory system design and verification, today announced that its Databahn™ memory controller cores are used in Azanda Network Devices Scimitar™ AZ61100 OC-48 Traffic Manager/ATM SAR. Azanda configured the on-chip Databahn memory controllers to provide 400 MHz data transfers from DDR-SDRAM memory devices operating at 200 MHz. Azanda's Scimitar chip performs traffic management and ATM segmentation and re-assembly (SAR) functions at full-duplex OC-48 speeds, delivering a total aggregate bandwidth of 5 gigabits per second (Gbps).
"Databahn is the most comprehensive IP solution available for high-speed memory system design," said Kevin Silver, vice president of marketing for Denali. "We're providing silicon-proven memory controller cores that are fully configurable to meet a broad range of performance and interface requirements, and we support our customers with everything necessary for successful implementation--from pre-hardened memory PHY cores, to specialized I/O pads. Azanda's success with Databahn in its Scimitar product is yet another example of how our IP infrastructure can deliver memory systems for even the highest-bandwidth applications."
"We have had great success with Denali's Databahn memory controller in our networking SAR & Traffic Manager products," said Kaushik Patel, vice president of engineering at Azanda Network Devices. "The quality of customer support and turnaround time on technical issues was outstanding. We configured the Databahn core for a 64-bit interface to DDR-SDRAM running at 200 MHz, and it was fully functional at speed in first silicon. Based on our success with the Databahn in our Scimitar™ chips, we have chosen to use Denali memory controllers in our next generation Saber™ product family of Traffic Managers and ATM SARs."
The Databahn solution enables designers to customize a memory controller core to meet performance and interface requirements for their ASIC application. Customization is supported through an online infrastructure at Denali's eMemory.com site. A browser-based GUI enables fast efficient configuration of various performance and interface options, and also enables simulation-based performance validation. To ensure compatibility with all the latest high-speed memory technologies, the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest DDRII-SDRAM, DDR-SDRAM, FCRAM, RLDRAM, and DDR/QDR-SRAM devices. Deliverables include: RTL and synthesis scripts, verification testbench, static timing analysis (STA) scripts, programmable register settings, and documentation. The silicon-proven Databahn IP is library independent and covers solutions from .18-micron to .08-micron technologies, and DRAM device frequencies from 100-400MHz (200-800MHz data rate).
About Denali Software, Inc.
Denali Software, Inc. is the world's largest provider of semiconductor intellectual property (SIP) and engineering design automation (EDA) tools for memory system design and verification. Denali's eMemory.com houses the industry's largest database of memory component information, and provides an online infrastructure for memory selection, memory controller IP configuration, and memory model access. More than 400 companies worldwide use Denali's EDA tools, semiconductor IP, and memory market information services to plan and develop memory systems for communications, consumer, and computing products. For more information, please visit Denali at www.denali.com or contact Denali directly at: 650/461-7200, or email: email@example.com
Note to Editors: Databahn and eMemory are trademarks of Denali Software, Inc., all other trademarks are the property of thier respective owners.