Automatically fixes netlist pessimism to eliminate major obstacle to successful gate-level simulation
SUNNYVALE, CA -- May 30, 2018 - Real Intent, a leading provider of SoC and FPGA sign-off verification solutions, today launched Verix SimFix, the first intent-driven verification remedy for gate-level simulation (GLS) of digital designs. Verix SimFix automatically eliminates X-pessimism, the major obstacle to successful GLS and boosts productivity for SoC design teams. It also extends Real Intent's product leadership in delivering the industry's fastest performance, highest capacity, and most productive verification solutions in the market.
Verification engineers know that GLS treats unknown values Xs pessimistically and produces results which do not represent actual hardware and causes undesired inconsistencies with the RTL analysis of the same design. Sign-off can take months.
SimFix relies on Real Intent's static intent-driven technology to discover X trouble spots in minutes for circuit blocks and only an hour for full-chip SoCs, by partitioning analysis across multiple compute servers. With Verix SimFix, unnecessary verification overhead during simulation is eliminated in the presence of Xs, so design teams can more quickly verify and sign-off on correct operation for implementation and manufacture.
Verix SimFix has a simple use model, providing best-in-class performance in both the static pessimism analysis and the associated simulation X-correction. Verification teams do not have to use inaccurate random initialization, simulator X correcting switches, nor deal with the overhead of synthesis options to prevent pessimism.
"Verification teams are looking for an easy-to-use, scalable, low-overhead, and deterministic solution to X-pessimism," stated Prakash Narain, founder and CEO of Real Intent. "The low-touch approach of Verix SimFix eliminates the need for synthesis changes or performance killing simulation options. It creates the right fix, in the right circuit location, on the fly, with fractional overhead during simulation. For large circuit blocks and full-chip SoCs, Verix SimFix is the only scalable solution for successful gate-level simulation".
For more on Verix SimFix, please visit the Verix SimFix product page.
Verix SimFix is available now. Pricing depends on product configuration.
About Real Intent
Real Intent is the industry leader in static sign-off of digital designs. Companies worldwide rely on Real Intent's EDA software to accelerate early functional verification and sign-off at RTL as well as gate-level. Its intent-driven static technology powers solutions for clock and reset domain crossing analysis (CDC, RDC), and cleaned RTL code and X-pessimism correction, to ensure design success for SoCs and FPGAs. Real Intent products lead the market in performance, capacity and accuracy, and provide a faster time to tape out. Please visit www.realintent.com for more information.