Synapse 3220 Employs Non-blocking Transaction Protocol and Enables Rapid Development of "Tiles" to Support Platform-based SOC Designs
Mountain View, California - 2002/12/02 - Semiconductor intellectual property (IP) provider Sonics, Inc. today introduced Synapse 3220™, a new product in its family of SMART interconnect intellectual property. Synapse 3220 is targeted at servicing a large number of peripheral IP cores physically dispersed across the die of complex SOCs (system-on-chip). Synapse 3220 complements Sonics' SiliconBackplane MicroNetwork™ and MemMax™ memory scheduler and enhances the Sonics Methodology and Architecture for Rapid Time to market (SMART) of SOC-based products.
Synapse 3220 includes a number of innovative and unique features that Synapse 3220's capabilities allow SOC designers to experience greater architectural freedom, faster time-to-market, lower power consumption, lower development costs, increased on-chip security, and better reusability of larger SOC design components than previously possible.
"The number of IP cores being designed into today's SOCs is raising the design complexity beyond the ability of current bus-based approaches to effectively handle the on-chip communications," said Dave Lautzenheiser, vice president of marketing at Sonics. "This is particularly true in digital multi-media type systems where there may be 5 to 10 initiator cores sending traffic to over 20 targets with greatly varying performance levels from low to medium to high. Synapse 3220 is a key ingredient in our solution that gives system architects more freedom to partition peripheral communication independent of physical design constraints."
Non-blocking Transaction Protocol
In classical bus-based architectures, communications with on-chip peripheral cores use a blocking protocol. Specifically, while a transfer is underway between any single initiator and target, the bus resources are not available for any other transfers to occur.
For example, a common "blocking" problem in today's traditional bus-based SOCs is related to DMA. While a multi-word DMA transaction is underway, no other initiator can access any of the other peripherals on the bus. This condition impairs the performance of the chip and has an impact on the size of buffers that must be added to the initiator to compensate for this low quality of service. Also, due to the variable, indeterminate length of DMA transfers, real-time performance is seriously impacted, causing "wait states" that ultimately degrade the end-user experience.
Conversely, Synapse 3220 features a non-blocking transaction protocol over a pre-verified interconnect architecture. This enables multiple individual initiator-target transactions to occur concurrently across the interconnect structure with deterministic response times. This architectural approach improves performance while removing the need for large buffers.
Synapse 3220 utilizes configurable agent technology and the Open Core Protocol (OCP) industry-standard socket to decouple the interconnect communication from the core computation, so architects can now partition and easily scale peripheral subsystems to take a product to a complete family in the shortest possible time. Because Synapse 3220 delivers communication that is of a deterministic nature, real-time application requirements, such as those often found in digital multi-media systems, can also be met.
To address critical power consumption issues in today's SOC designs, Synapse 3220 features a low-power architecture and fine grained power management to give designers the freedom to make informed trade-offs between the placement of cores, overall interconnect power budget, and die area cost.
For protection of system integrity and media content passed between on-chip processing blocks and various I/Os and the memory subsystem, Synapse 3220 provides an on-chip programmable security "firewall" capability. IP cores can be selectively physically connected, but electrically isolated on the die.
Platform-based SOC Design with Tiles
Synapse 3220 is part of the complete Sonics SOC design architecture and methodology (SMART) that dramatically shortens time-to-market for complex SOC products. The Sonics platform-based SOC methodology represents a new level of abstraction-a level of hierarchy that reduces the number of objects that designers must effectively manage by creating a set of independent subsystem "tiles." A tile is a collection of functions requiring minimal assistance from the rest of the die. Frequently including an embedded processing unit, local memory, and relevant I/O resources, a tile is architected for reuse without rework multiple times in the same SOC or across an SOC product family. (See Sonics' white paper entitled "SMART Interconnect Technology: Fulfilling the Promise of Design Reuse" for more information on tiles and SMART.)
Pricing and Availability
Synapse 3220 includes the pre-verified interconnect IP, behavioral simulation models, and graphical SOCCreator development environment for architectural modeling, IP configuration, and automatic RTL generation. It is available for license immediately priced at $120,000 U.S. list.
About Sonics, Inc.
Sonics, Inc. is a premier developer of intelligent semiconductor intellectual property (IP) solutions that dramatically accelerate complex system-on-chip (SOC) designs while minimizing risk. The Sonics Methodology and Architecture for Rapid Time-to market (SMART ) initiative is a comprehensive collection of products, services and partnerships to ensure customer success when utilizing Sonics SMART interconnect IP. SMART users can develop devices with higher functionality, lower power consumption and lower cost while achieving greater SOC complexity faster. Major semiconductor and systems companies have embraced Sonics SMART products for SOC applications in the communications, networking and multimedia markets, often reporting better than six-month design time savings with reduced design and manufacturing risks. For more information, see www.sonicsinc.com.