Configurability of industry’s lowest-area, lowest-power core provided optimal solution for eSilicon
SAN MATEO, Calif. and SAN JOSE, Calif. – Aug. 7, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, and eSilicon, an independent provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, today announced that, after extensive review and testing of available options in the market, eSilicon has selected the SiFive E2 Core IP Series as the best solution for its next-generation SerDes IP at 7nm.
eSilicon’s 7nm SerDes IP represents a new breed of performance and versatility based on a novel DSP-based architecture. Two 7nm PHYs support 56G and 112G NRZ/PAM4 operation to provide the best power efficiency tradeoffs for server, fabric and line-card applications. The clocking architecture provides extreme flexibility to support multi-link and multi-rate operations per SerDes lane.
“Today’s high-performance networking applications require the ability to balance power and density to effectively address increasing performance demands,” said Hugh Durdan, vice president of strategy and products at eSilicon. “SiFive’s E2 Core IP allows eSilicon to provide the flexibility and configurability that our customers require while achieving industry-leading power, performance, and area.”
The SiFive E2 Core IP is designed for markets that require extremely low-cost, low-power computing, but can benefit from being fully integrated within the RISC-V software ecosystem. At one-third the area and one-third the power consumption of similar competitor cores, the SiFive E2 Core series is the natural selection for companies like eSilicon that are looking to address the challenges of advanced ASIC designs.
“eSilicon has a successful track record for leveraging the most advanced technologies to develop high-bandwidth, power-efficient IP for ASIC design,” said Brad Holtzinger, vice president of sales, SiFive. “Our E2 Core Series IP takes advantage of the inherent scalability of RISC-V to bring the highest performance possible to the demands of advanced ASICs. We look forward to working with eSilicon on its next-generation SerDes to address these demands.”
SiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Huami, SK Telecom, Western Digital and Intel Capital. For more information, visit www.sifive.com.
eSilicon is an independent provider of complex FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete 2.5D/HBM2 and TCAM platforms for FinFET technology at 16/14/7nm as well as SerDes, specialized memory compilers and I/O libraries. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com