SAN MATEO, Calif. Once thought of as paying only lip service to FPGA tools, Synopsys Inc. is now acting like a serious player in high-end FPGA design. The company recently announced it has developed links that will allow its formal verification, static timing and rule-checking ASIC tools to work with Xilinx Inc.'s ISE 4.1i tool suite, and is otherwise making forays into the FPGA tool market.
But competitors and Gartner Dataquest analyst Gary Smith said the company may have a hard time passing Synplicity and Mentor Graphics, both of which jumped on the FPGA market opportunity early and are developing new technologies to capitalize on it.
Synopsys is taking direct aim at the high-end FPGA tool space and especially Synplicity's market share lead, said Jackie Patterson, director of marketing programs for register transfer level (RTL) synthesis at Synopsys. The Mountain View, Calif., company is bringing more of its ASIC tool expertise into the high-end FPGA flow, she said.
"We have increased our investment in high-end FPGA, not only in synthesis but across the broad spectrum of tools," said Patterson. "In past years we were competing with one arm tied behind our back, and now we are attacking it with our full ASIC flow and capabilities. We will see even more changes going forward."
At the same time, Synopsys is deemphasizing its entry-level FPGA synthesis tool, FPGA Express. Altera Corp. did not renew its contract to OEM FPGA Express, leaving Xilinx the only reseller of the product. And Synopsys no longer offers a version of FPGA Express supporting all FPGA vendors.
Synplicity Inc., which at one time offered stripped-down OEM versions of its Synplify tool, is now also going after the high-end FPGA market. Indeed, it appears that Synplicity's introduction of an ASIC synthesis tool to compete with Synopsys' Design Compiler at the Design Automation Conference in June is what woke the sleeping giant.
"Synplicity should be or certain ly will soon be aware that we are taking high-end FPGA seriously," said Patterson.
Andy Haines, vice president of marketing for Synplicity, doesn't see Synopsys as a threat. Haines pointed out that the company's high-end FPGA synthesis tool, Synplify Pro, which has been out for only a year, owns the high-end synthesis market-share lead. Synopsys' FPGA Compiler II has been on the market since 1998.
"Synopsys is identifying this as a big market a bit late in the game," said Haines. "But I guess the saying is true, 'Imitation is the sincerest form of flattery.' "
Haines said that Synplify Pro also has capabilities, such as physical synthesis, that FPGA Compiler II lacks.
Though Smith, who is Gartner Dataquest's chief EDA analyst, has not published FPGA tool market share numbers for 2000, he said the tally will show that Synplicity has the "clear lead in FPGA synthesis," followed by Mentor Graphics' subsidiary Exemplar Logic Inc. and then Synopsys.
"Synplicity doubled its growth from 1999 t o 2000," said Smith, adding that Synopsys has "a tough row to hoe" to catch up with Synplicity and even Mentor.
"FPGA Compiler II was focused on the ASIC designer who wants to prototype an ASIC on a bunch of FPGAs," said Smith. "I don't hear about the tool much these days, and I think it competes more directly with Synplicity's prototyping tool, Certify."
The fact that "both Mentor and Synplicity have tools that can do both ASICs and FPGAs" represents "not only a threat to FPGA Compiler II but also to Design Compiler," Synopsys' ASIC tool, he said.
Haines said Synplicity isn't worried about losing Certify wins to FPGA Compiler II, either. "Certify has been used to transfer a $6.5 million-gate ASIC onto a bunch of FPGAs, so we certainly aren't worried about the capacity of our tools, and we've always had the best accuracy and performance," said Haines.
Synplicity, meanwhile, is still doing business with its mainstream version of Synplify, OEMing that product to Actel, Lattice Semiconductor a nd QuickLogic.
Mentor Graphics which has long supplied OEM versions of entry-level FPGA tools to vendors such as Actel, Altera, Xilinx and others is also investing in and stepping up development efforts on high-end tools. The company is currently working on a new approach to synthesis that it has dubbed "heuristic synthesis."
Its heuristic-synthesis tool, code-named Atlanta, will replace Exemplar's Leonardo Spectrum, said Anne Sanquini, senior vice president and general manager of Mentor's HDL division. Sanquini added that Exemplar will become Mentor's Synthesis Division.
The technology, which will hit beta testers in November, features automatic inferencing and incorporates static timing technology from Mentor's SST Velocity product.
"Automatic inferencing is a feature that reads the designer's intent," said Sanquini. "It does what a designer would do anyway, only better. Rather than synthesizing the code line by line, it will identify the user's coding style and what the u ser is creating a RAM, for example and ask the user if he want to use or call a preoptimized block of memory from the tool's library."
This feature, she said, will help the run-time of the tool and also increase a given device's performance, because the elements or blocks are preoptimized.
Sanquini declined to give further details, but said that Mentor has a road map to include several other technologies into the synthesis offering, beyond static timing and automatic inferencing.
She said that the new technology is a continuation of Mentor's efforts in FPGA design. "We didn't say 'OK, we'll just make this ASIC tool work with FPGAs,' " Sanquini said. "We work on the technology in terms of solving technology problems for the FPGA customer as well as giving them easy access to technologies that will make their job easier."
Among the ways Mentor helps FPGA designers, Sanquini said, is by customizing ASIC intellectual property for FPGA implementation and giving designers easy acce ss to these cores through the Common License Consortium.
Sanquini noted that Mentor does not have a single division simply dedicated to offering tools for the FPGA market. Rather, she said, the whole company is lending its technologies to the FPGA space.
Synopsys' Patterson said that designers working with large-gate-count FPGAs such as Xilinx's Virtex devices are requesting more sophisticated tools. She believes that as designers move from ASIC to FPGA, they will take a closer look the company's FPGA Compiler II, which she described as very similar to Synopsys' ASIC design tool, Design Compiler.
"FPGA designers confront more challenges than ever before," Patterson said. "Designers who have experience using our tools on the ASIC front want a similar and familiar tool suite on the FPGA front, as well."
Meanwhile, Synopsys hopes that its PrimeTime static timer will see growth in the FPGA space as programmable devices become more complex. That tool already owns a majority of market share in A SIC static timing, according to Gartner Dataquest.
And the sheer amount of code that designers produce for million-gate FPGAs is starting to rival that of ASICs, said Patterson, opening market opportunities for Synopsys' Leda RTL rule checker in FPGA design.
Patterson said that Synopsys is also working with Altera to integrate its ASIC tools into Altera's Quartus II flow. But with the demise of the OEM contract with Altera, Synopsys is encouraging users to move to FPGA Compiler II.
Patterson said the company is not phasing out its $2,500 FPGA Express tool altogether, but wants to put more emphasis on its high-end FPGA Compiler II, which starts at $12,000.
"Those who are really interested in good synthesis should be looking at our FPGA Compiler II product," said Patterson, who noted that it has been expensive for Synopsys to build two synthesis libraries one for each tool for each new programmable device.
Patterson said that while FPGA Express will not support future Altera devices, the Compiler II will.
Peter Woo, director of tools at Altera, said that it was a mutual agreement not to renew the OEM contract and that Altera maintains a good relationship with Synopsys, especially for linking Synopsys' high-end tools to Quartus II.
"We notified our users of FPGA Express about the change, and they can either get our version of [Exemplar's] Leonardo Spectrum or get Synopsys' FPGA Compiler II direct from Synopsys," said Woo.
Altera believes that working with a smaller number of third-party tool vendors will allow its internal tool-development group to better focus on maintaining quality flows for its customers, Woo said. Altera had problems with the first version of Quartus software, but Woo said that those problems have been straightened out now with Quartus II.