Sophia-Antipolis, FRANCE - (September 10th, 2001) - Tachys Technologies, a leading provider of advanced backplane interconnect technology, today unveiled its new high-speed serial data transmission technology. This technology will significantly increase the performance and reduce the cost of local area network (LAN) and wide area network (WAN) packet management hardware by lowering system power and heat requirements as well as circuit board design time.
Implemented in a .18 CMOS process, the link includes a serdes that transmits and receives data serially over two differential pairs, delivering a programmable, point-to-point full-duplex throughput of 1.0 to 3.2 Gbps, with the ability to run at full speed with less than 100 mW of power dissipation. The serdes embeds on-board clock generators and a programmable pre-emphasizer that counters signal distortion. In addition to the serdes, the technology implements a link-layer flow control mechanism that guarantees lossless transmission and provides backpressure, thus simplifying chipset and system architecture.
The technology will be ideal for applications that require chip-to-chip and board-to-board data transmission over printed circuit boards (PCB) or several meters of cabling, and in particular for high-throughput backplane interconnects and switch fabric subsystems found in LAN and WAN switches and concentrators.
About Tachys Technologies
Tachys Technologies is a leading provider of backplane interconnect technology that provides innovative, high-speed interconnect building blocks for data communications equipment. Tachys is headquartered in the heart of France's Telecom Valley in Sophia Antipolis. For more information please visit www.tachys.com or at Booth 6939 at Networld+Interop in Atlanta, September 11-13 th 2001.
For further Press information :
Tachys Technologies
Daniel Mayer
Director, Marketing
+33 4 97 23 41 73
dmayer@tachys.com