Update: Rambus Completes Acquisition of Northwest Logic, Extending Leadership in Interface IP (Aug. 27, 2019 )
The IP is silicon-proven with immediate availability
October 4, 2018 - Northwest Logic and Mixel® announced today that their MIPI® CSI-2SM and DSI-2SM solutions which utilize MIPI C-PHY SM / D-PHY SM have been deployed and silicon proven in 28nm, 40nm, 55nm and 65nm process nodes. These high performance, low power, cost effective solutions contain controllers from Northwest Logic and PHYs from Mixel.
MIPI C-PHY uses symbol encoding (2.28 bits per symbol) to transmit data on 3-wire lanes “trios”. Three trios operating at 2.5 Gsym/s/trio provides a peak data rate of 17.1 Gbps over 9 pins. In contrast, four D-PHY data lanes with one clock lane operating at 2.5 Gbit/s/lane provides a peak data rate of 10 Gbps over 10 pins. Eliminating the separate clock lane enables the trios to be easily assignable to different links and eliminates clock lane emissions. C-PHY also provides 12% lower toggle rates/lane with 20-50% lower power.
Northwest Logic, is a market leader in digital controllers including CSI-2, DSI-2, HBM2, GDDR6 and PCI Express. Northwest Logic’s CSI-2 and DSI-2 controllers support all of the features needed in today and tomorrow’s MIPI applications including the latest CSI-2 and DSI-2 specifications, Host (Tx) and Peripheral (Rx) operation, and multiple user interface and core width options. The MIPI controllers are highly configurable while achieving low power, small size and ease of use. These controllers have been widely used in both ASICs and FPGAs with more than 160 design wins. This includes automotive LIDAR/RADAR, Image Signal Processor (ISP), Virtual Reality (VR), camera and many other applications.
Mixel is the market leader in MIPI PHYs. Mixel’s Combo C-PHY/D-PHY can be configured as a MIPI Tx (Host) or Rx (Peripheral) supporting CSI-2 v1.3 (Camera Serial Interface) or DSI-2 v1.0 (Display Serial Interface) applications. The Combo C-PHY/D-PHY reuses the same pins for C-PHY and D-PHY operation. Mixel's implementation maximizes reuse between D-PHY and C-PHY modes, minimizing area and leakage power and ensuring a smooth D-PHY to C-PHY transition.
“We are seeing growing adoption of our C-PHY/D-PHY combined solution in customer designs,” said Ashraf Takla, Mixel’s President and CEO. “Our initial C-PHY/D-PHY customers considered the C-PHY a nice option to have. Now they see the C-PHY support as a competitive feature that is key to the viability of their product. This bodes well for the C-PHY adoption and for Mixel and Northwast Logic’s leadership position.”
“Northwest Logic and Mixel have collaborated to provide fully integrated and validated MIPI controller + PHY solutions. This combined solution is silicon proven with 40 mutual MIPI design wins, all tape-outs first time silicon successful, and a growing list of CSI-2 and DSI-2 C-PHY/D-PHY deployments,” said Brian Daellenbach, Northwest Logic’s President.
About Northwest Logic
Northwest Logic, founded in 1995 and located in Hillsboro, Oregon, provides high-performance, silicon-proven, easy-to-use IP cores including high-performance Memory Interface Solution (DDR4/3/2, LPDDR3/2/1, RLDRAM 3/II), Expresso Solution (PCI Express 3.0/2.1/1.1 cores and drivers including DMA support), and MIPI Solution (MIPI® CSI-2SM, DSI-2SM). These solutions support a full range of platforms including ASICs, Structured ASICs and FPGAs. For additional information, visit www.nwlogic.com or contact email@example.com.
Mixel is the leader in mixed-signal mobile IPs and offers a wide portfolio of high-performance
mixed-signal connectivity IP solutions. Mixel’s mixed-signal portfolio includes PHYs and SerDes,
such as Mobile PHYs (MIPI® D-PHYSM, M-PHY®, C-PHYSM and LVDS), and high-performance
PLL and DLL IP cores. For more information contact Mixel at firstname.lastname@example.org or visit www.mixel.com.