Grenoble, October 8, 2018 -- Designing an energy-efficient SoC is a challenge: it requires different specific skills all along the design flow, from the architectural step up to the physical implementation, in order to save every possible µA in both active and sleep mode.
Low-power design techniques have been deployed in mature processes, specifically related to the integration of the power regulation network. But migrating to advanced nodes comes up with new leakage challenges to meet stringent energy-efficient expectations from the market.
After a short description of the low-power techniques, this live webinar illustrates, through a concrete example, a methodological approach to identify the optimal power architecture. It also unveils new solutions to design cost-effectively and safely an energy efficient SoC using an advanced process.
Register to this live webinar.
During this webinar, SoC architects, designers, project leaders, and design methodology managers will go through the following agenda:
Vision on the constant need to improve energy efficiency with an overview of the low-power design technics to meet the market needs
Methodology to explore and compare objectively the worth of SoC power architectures – illustration on a BLE application
Focus on some technical challenges with advanced process nodes - highlight on specific solutions to leverage unique FD-SOI process capabilities for minimizing SoC power consumption
Introduction of a complete and consistent Power Management IP platform enabling to select and implement easily and safely advanced low-power design techniques
This webinar will be held several times:
- For EU Time zone: October 16
- For US Time zone: October 25
A session in Mandarin is planned on October 25. Register to the Mandarin session by following this link.
If you want to watch the record of our previous webinars « The proven recipe for a low-power SoC » or « How to get an SoC power consumption under 0.5 µA in sleep mode », you can ask for an access to MyDolphin.
For any other information on these webinars, you can contact Aurélie Descombes, Communication Manager.
About Dolphin Integration
Dolphin Integration is a pioneer in Energy-Efficient Systems-on-Chip enablement. The company serves a growing range of applications from battery-operated to line-powered. Its portfolio of more than 200 silicon IPs covering Foundation, Feature and power Fabric IPs are proven and available in multiple processes and foundries. This coherent portfolio allows to reduce SoC power consumption in sleep, triggering and active processing modes. The company is committed to its customer success through constant innovation, quality control and dedicated support. Dolphin Integration comes with 30 years experience in integration of silicon IP components leveraging power-integrity driven simulation tools to design and supply cost-effective logic and mixed-signal ASIC/SoC.