Imperas leading virtual platform simulation technology combined with Valtrix leading verification technology for rigorous RISC-V Processor test developments, verification and compliance.
RISC-V Summit, Santa Clara, Calif., December 3, 2018 — Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced the partnership with Valtrix Systems for advanced RISC-V Processor test and validation. STING, the flagship product of Valtrix Systems, is a highly versatile bare-metal software tool for design verification of SoC implementations. Implemented in an architecture agnostic manner, it supports generation of constrained random, directed or graph-based portable stimulus for multiple IPs. Valtrix have integrated STING with riscvOVPsim, the free RISC-V ISS (Instruction Set Simulator) Imperas has launched to support RISC-V software and tools ecosystem development, and to validate and test RISC-V open ISA (Instruction Set Architecture) implementations. With this partnership Valtrix can configure virtual platforms as a verification reference as well as extending the RISC-V envelope model with custom instructions.
“We are encouraged by the developments with STING around riscvOVPsim for RISC-V processors to solve complex test and verification based on commercial grade simulation technology,” said Simon Davidmann, president and CEO, Imperas. “The strength of an ecosystem is close collaborations between partners that lead to better solutions for our mutual customers. With this expanded relationship Valtrix can address RISC-V implementations with custom instructions and model complete RISC-V processor sub-systems as reference virtual platforms.”
Shubhodeep Roy Choudhury, Managing Director & Co-founder, Valtrix, commented: “Test and verification of RISC-V open ISA cores is the most demanding challenge for processor developers today. By partnering with Imperas and using the OVP virtual library of platforms we can offer customers a complete solution across all aspects of RISC-V processor verification, test and compliance.”
The software stack of STING is specially designed to serve as a platform for the design verification of IP/SoC implementations. In addition to a vast architectural verification test suite, STING also provides powerful programming frameworks to users for test development customized for their implementation. The tests are then compiled with bare metal kernel and libraries into a portable program as per the needs of the verification environment. The program can seamlessly boot on simulation, FPGA prototypes, emulation or silicon and execute different testing workloads that the user programs or requests for.
Both Imperas and Valtrix will be exhibiting at the Inaugural RISC-V Summit, December 3-6 2018, Santa Clara, California, USA. Imperas will also deliver a presentation on RISC-V compliance in the era of open ISA and custom instructions.
More details and registration discount codes are available at Imperas.com.
Valtrix Systems is the trading name of Valtrix Technologies Private Limited, which was formed with a mission of creating world class tools and testing methodologies that will help companies efficiently verify the designs of IPs and SoCs. The founding team comprises of system validation veterans who bring with them many year's of experience of validating complex microprocessor/system functionalities.
To address all the challenges imposed by the design verification requirements, Valtrix Systems is coming up with a family of products to increase the productivity of verification engineers, enable reuse of testing infrastructure and achieve coverage goals quickly.
For more information about Valtrix, please visit http://valtrix.in. Follow Valtrix on LinkedIn and Twitter.
Imperas is revolutionizing the development of embedded software and systems and is the leading independent provider of processor models and virtual prototype solutions. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. The OVP library includes models for Arm, MIPS, Synopsys ARC, RISC-V, and other standard and proprietary CPU architectures, plus peripheral models and many reference example platforms. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.