Event debuts cores, FPGA, AI chips, interconnect
By Rick Merritt, EETimes
December 4, 2018
SAN JOSE, Calif. — RISC-V is open for business, proponents will claim at the first annual summit for the open-source instruction set architecture today. The Silicon Valley event comes at a time when backers say that China is rallying around the architecture with perhaps hundreds of RISC-V SoCs and dozens of cores in the works.
At the event, Western Digital will detail a 32-bit embedded core that it will use in a controller for a consumer solid-state drive set to ship in 2020. It is releasing as open-source both the core and a protocol for a cache-coherent interconnect for RISC-V processors — and it has started work on a 64-bit core.
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