SAN JOSE, Calif. The newly-published third edition of the Reuse Methodology Manual (RMM), a seminal text that defines a comprehensive approach to intellectual property (IP) reuse in chip designs, includes new material on the experiences of six companies regarding their system-on-chip (SoC) design flows and IP reuse.
In a new chapter of the RMM, design managers from Alcatel, Atmel, Infineon Technologies, LSI Logic, Philips Semiconductors and STMicroelectronics each discuss their SoC design flows and provide block diagrams depicting those flows. They also talk about some of the challenges they've experienced in trying to implement design reuse.
First published in 1998 with backing from Synopsys Inc. and Mentor Graphics Corp., the RMM was hailed as a definitive text that set forth a new SoC design flow. The RMM includes descriptions of system-level design, RTL coding guidelines, and approaches to developing and integrating reusable hard a nd soft IP blocks.
But much has changed since the first two editions of the RMM were published in 1998 and 1999, said Pierre Bricaud, director of R&D for IP and design solutions at Synopsys and co-author of the book, along with Michael Keating. "IP reuse is now a reality," he said. "In the first edition, we were using the future tense for verbs, and how we're saying that this is the way it's done."
In the new edition of the RMM, Thierry Pfirsch, core program manager in the hardware coordination division at Alcatel, says his company used an internal Web site to exchange information about IP. He describes a program that helps Alcatel select external IP, and an in-house "evaluation service" that provides a report for each IP block.
Erich Palm, director of libraries and design tools for Atmel Corp., says his company uses a "concurrent" SoC engineering flow that encompasses both chip and applications design. A new design based on Atmel IP takes around six to nine months, he says.
Infineon Technolo gies AG has a "very stable and robust" SoC design flow, says Albert Stritter, vice president for design automation and technology at Infineon. But more help is needed, he says. "We currently see, however, with the advent of very deep submicron technologies, that a new paradigm shift for the complete flow is necessary," Stritter says. "The EDA offerings are lagging behind some years."
LSI Logic Corp.'s flow separates logical from physical design, but there's a growing need to exchange information between the two, says Tim Daniels, technical product marketing manager for LSI Logic's U.K. ASIC division. He provides examples of LSI Logic's RTL coding rules, many derived from the RMM.
Philips Semiconductors' design flow emphasizes the use of emulation for verification, says Louis Quere, IC development manager at Philips. And STMicroelectronics has developed a "top-down, block-based approach" with clean interface points, according to Thierry Bauchon, director of R&D for that companys' set-top box division.
Signs of age
The third edition of the RMM updates references to standard SoC buses and removes references to specific EDA tools. Elsewhere, examples have been updated to reflect the widespread use of the ARM Ltd.'s Amba bus and IBM's CoreConnect technology, Bricaud said. The first two editions used more "generic" examples.
Bricaud said he believes the third edition of the RMM will be the last. "This is the way you design down to 130 nanometers with IP reuse," he said. "But now we're going to 90 nm, and there are going to be dramatic changes in the design methodology. Physical effects are going to have to be taken into account early in the design cycle, and we don't have all the solutions."
The third edition of the RMM is available from Kluwer Publishing priced at $135.