Revamped Software/Hardware Interface for Multicore/Manycore (SHIM) Processors Enables Accurate Representation of Performance and Power Modeling
EL DORADO HILLS, Calif -- January 23, 2019 -- The Multicore Association™ (MCA), a global non-profit organization that develops standards to optimize products with multicore processor implementations, announced today that it has released an updated version of its Software/Hardware Interface for Multicore/Manycore (SHIM) processors and tools. SHIM version 1.0, which was available in 2015, is a specification that helps existing software tools quickly adapt to new hardware and accelerates the development of new innovative tools. SHIM 2.0 includes enhanced capabilities for complex processor architectures and improved performance estimation accuracy.
SHIM’s primary goal is to define an architecture description standard useful for software design (analogous to the hardware description format called IP-XACT, which is used for hardware design). Some architectural features that SHIM describes include processor cores, accelerators, memory/caches, and inter-core communication channels – providing details such as instruction, memory, and communication performance information.
“The SHIM standard is beneficial for many types of tools, including performance estimation for parallelization tools, hardware modeling, and system configuration,” said Masaki Gondo, CTO at eSOL and chair of the SHIM working group of the Multicore Association. “Performance information is critical for most software development tools, including performance analysis and optimization tools and auto-parallelizing tools.”
SHIM 2.0 models state-of-the art processors including heterogeneous functional units, pipelining effects, and 32-bits vs. 64-bits, and single-instruction-multiple-data instructions (SIMD). This capability allows the description of complex DSPs, hardware accelerators, and soft cores. The SHIM 2.0 also supports more accurate modeling of power consumption, allowing the use of different voltages and frequencies associated with individual processor or clusters.
“With the continued acceleration in the use of multicore and heterogeneous computing, the SHIM 2.0 standard will strengthen the development options for embedded engineers at the edge,” said Maximilian Odendahl, CEO of Silexica, which has been a major contributor to the SHIM 2.0 project. “SHIM 2.0 will enable Silexica to replace the proprietary platform model with a standardized one while keeping all of the existing features. This means SHIM 2.0 combines the best of SHIM 1.0 and Silexica's platform model to support multicore development in the future."
The SHIM 2.0 specification is publicly available from the organization's website. For more information, visit http://www.multicore-association.org/workgroup/shim.php.
About The Multicore Association
The Multicore Association provides a neutral forum for vendors interested in, working with, and/or proliferating multicore-related products, including processors, infrastructure, devices, software, and applications. The consortium has made freely available its SHIM, Multicore Communications API (MCAPI) Multicore Resource Management API (MRAPI), and Multicore Task Management (MTAPI) specifications, as well as its Multicore Programming Practices (MPP) guide. In addition to the SHIM working group, the organization has active working groups focused on Multicore Communications (Version 3.x). Further information is available at http://www.multicore-association.org.