SerDes test system addresses the demands of 56/112G PAM4 operation using upcoming IEEE P370 standard
SANTA CLARA, Calif. — January 30, 2018 — eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, in collaboration with Wild River Technology, announced today at DesignCon 2019 the availability of an advanced test system that addresses the incredible signal integrity demands of 56/112G PAM4 operation.
High baud-rate PAM4 test/characterization systems are challenging to design due to the high demands for superior signal integrity and signal-to-noise ratio (SNR). The test system design utilizes the upcoming IEEE P370 standard in association with compliance metrics 802.3bs, OIF CEI – 56G PAM4, and COBO to validate the required performance. Keysight’s Advanced Design System was used to explore power spectral density, examining how much bandwidth is needed for effective testing and what specific metrics of IEEE P370 are most important, such as return loss, equivalent return loss, time-domain reflectometry (TDR) and impedance analysis. eSilicon’s 56G PAM4 & NRZ DSP-based 7nm SerDes was used to drive the communication channels.
The design employed a channel-modeling platform to improve de-embedding quality out past 70GHz, establishing clear targets of equalization and creating an advanced reference design suited for immediate 3D electromagnetic design. The core of the design was Samtec’s Bulls Eye® Test Point System. Three independent teams worked on the design. Two teams were resident at Wild River and used the ANSYS® HFSS™ and Simbeor® THz software, respectively. A third team was resident at Samtec.
eSilicon & Wild River Technology advanced SerDes test system will be demonstrated at DesignCon 2019 in Samtec booth #737: >2Tbps through >5 meters of copper cable
“Our design approach reduced spins and shortened schedules, allowing us to achieve conformance to the emerging IEEE P370 standard through a systematic design methodology,” said Al Neves, founder and CTO at Wild River Technology. “I got the idea for this approach from the early Apollo missions where they calculated launch trajectories with three teams working independently and concurrently. We all know this resulted in success for the Apollo program and it has resulted in success for our test system design as well.”
“We are delighted with this test system design — our next phase is to design and build a test socket suited for 70GHz,” said David Axelrad, senior director of IP marketing at eSilicon. “There are only a few companies that have silicon working at these speeds, and eSilicon is focused on being the first in production with a true long-reach DSP SerDes in 7nm.”
eSilicon will be demonstrating its 56G PAM4 & NRZ DSP-based 7nm SerDes at Samtec booth #737 at DesignCon 2019.
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com