February 12, 2019, San Jose, Calif.
eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, is presenting a paper at the International Solid-State Circuits Conference (ISSCC) and is demonstrating eSilicon’s 7nm 56G full-DSP SerDes over a five-meter Samtec cable assembly.
Paper Presentation and Live Demonstration:
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET
eSilicon will show a low-power, long-reach DSP SerDes operating continuously over 1-56 Gb/s. The ADC/DAC-based transceiver is capable of equalizing channels with more than 42 dB of insertion loss, achieving a power efficiency of 4.34 pJ/bit. The demo session will show system operation at 53.125 Gb/s PAM-4 with a BER better than 10-10 over a 5m cable provided by Samtec, which provides an overall insertion loss of 35.2 dB bump-to-bump.
The paper and demonstration will be presented by Matteo Pisati, senior manager, analog IC design; Paolo Pascale, senior manager SerDes digital; and Fernando De Bernardinis, senior system and algorithm manager. Additional authors include Claudio Nani, Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti, Massimo Cutrupi, Andrea Rossini, Roberto Massolini, Giovanni Cesura, and Ivan Bietti, all of eSilicon Italy in Pavia, Italy.
When & Where:
Monday, February 18, 2019
2:30-3:00 PM paper presentation, Session 6.3
5:00-7:00 PM demonstration
San Francisco Marriott Marquis
ISSCC is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency, and to network with leading experts. February 17-21, 2019, San Francisco, California.
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com