Best-in-class IP and multiple FinFET/2.5D product bring-up programs set a rapid pace
SAN JOSE, Calif. — February 14, 2019 — eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the achievement of multiple milestones related to the company’s growth in the tier one FinFET ASIC market, serving high-bandwidth networking, high-performance computing, AI and 5G infrastructure.
Critical requirements to serve these markets include leading-edge, high-performance, differentiating semiconductor IP that is validated in advanced process nodes, a track record of successful design and fabrication of complex, FinFET-class ASICs and expertise in the design and manufacture of 2.5D package assemblies, including the integration of HBM memory stacks.
In the fall of last year, eSilicon announced availability of its neuASICä IP platform for AI ASIC design. The innovative IP platform includes an HBM2 PHY and AI mega/giga cells, including a convolution engine and accelerator builder software, all verified in 7nm technology. In that same time frame, the company announced that its 56G long-reach 7nm DSP SerDes was available for licensing.
In January, 2019, eSilicon announced a new high-performance test system to facilitate customer validation of its SerDes IP. At the recent DesignCon show, eSilicon demonstrated the new test system and its SerDes driving a five-meter copper cable at 56Gbps with very low error rates. Several customer engagements are underway with this SerDes IP, and customer feedback is validating its best-in-class capabilities. Also in January, eSilicon announced the formation of a technical advisory board for its AI initiatives staffed by three prominent technologists from academia and industry.
The company is in active production bring-up with two FinFET designs, including 2.5D technology utilizing its HBM2 PHY. All performance parameters are being met and both designs are on track to achieve full-scale production this year. One of the designs represents the largest ASIC eSilicon has ever built. It is believed to be the largest chip the foundry has ever produced as well.
“Our customers demand best-in-class IP, advanced ASIC and packaging expertise and the resources and technical depth to facilitate production bring-up of the final device,” said Hugh Durdan, vice president of strategy and products at eSilicon. “I am pleased to say we are delivering on all fronts. Recently, a tier one customer reported that they were usually quite critical of all IP. They went on to say they could find nothing to criticize after detailed evaluation of our SerDes.”
eSilicon will be presenting “A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET” at ISSCC in San Francisco on February 18. The company will be demonstrating its SerDes live at ISSCC that day as well. You can also find eSilicon at OFC in San Diego from March 5-7 (booth #5416), where the company will present two high-speed SerDes demonstrations and a demonstration if its HBM2 PHY.
You can learn more about eSilicon’s FinFET ASIC capabilities here, its advanced networking IP platforms here or its neuASIC AI platform here. To probe further, contact your eSilicon sales representative directly or via firstname.lastname@example.org.
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com