By Regina Freed, Applied Materials
EETimes (March 4, 2019)
For past semiconductor technology nodes, the industry took for granted that the edges of features within a chip could, for practical purposes, be considered straight and reasonably well aligned to other feature edges from layer to layer. But as dimensions shrink, the allowable tolerance for edge placement error (EPE), which refers to the vertical misalignment of features, has also shrunk and those past assumptions are no longer valid.
In advanced multi-layer chip designs and with chips getting smaller for emerging packaging schemes, EPE poses an unacceptable limitation on yield, and traditional methods of aligning feature edges are inadequate. This difficulty affects (intermediate) edges defined by photolithography, deposition and etch processes that produce a single final edge, as well as alignment between layers--for example, between metal 1, metal 2 and the vias that connect them. Even the smoothness of a final edge is now a potential error issue impacting alignment.
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