HSINCHU, TAIWAN – March 18, 2019 – As the first public CPU IP company in Asia, specializing in low-power, high-performance 32/64-bit processor IP cores and SoC design platform, Andes Technology Corporation (TWSE:6533) created a RISC-V promotion program called the “EasyStart” in July, 2018. The goal of the RISC-V EasyStart program is to help Andes’ design service partners catch the emerging opportunity in RISC-V based SoC design and development. The expanding global alliance now has 15 members and is on the way to its target 20 members in the near future.
The alliance in alphabetical order includes Alchip, ASIC Land, BaySand, CMSC, EE solution, INVECAS, MooreElite, PGC, SiEn (Qingdao) Semiconductor, Silex Insight, Socle , XtremeEDA and 3 unnamed partners. These companies cover foundry process technologies from 90nm to 10nm and some provide both SoC design and turn-key service. The alliance partners will use Andes qualified V5 RISC-V processor cores to provide their end customers total RISC-V design service solutions.
Andes has over ten years of professional experience in designing high-performance/low-power, 32/64-bit processor cores. Shipment of AndesCore™ embedded in customer SoCs in 2018 reaches one billion mark and the cumulative total volume surpasses 3.5 billion. One of RISC-V architecture’s merits is its extensibility. As a founding member of the RISC-V Foundation, Andes is dedicated to bringing its expertise in developing CPU processor cores to enhancing the RISC-V ISA. For example, the AndeStar™ V5, Andes’ fifth generation architecture, extends RISC-V ISA with features developed over the past 13 years. As the chair of the RISC-V P-extension (Packed SIMD/DSP) Task Group, Andes contributed its DSP ISA used in its successful D10 and D15 processors as the standard draft. As co-chair of Fast Interrupt Task Group, Andes is also proposing its extension to be part of the RISC-V standard. In addition, Andes is a major maintainer and contributor of the RISC-V open source software, including compilers, libraries, debuggers, and the Linux kernel. With its technical expertise and innovation, Andes is leading the empowerment of the RISC-V community.
About the Andes V5 family processors
Andes V5 family processors include the 32/64-bit N25F/NX25F for general purpose or floating-point intensive applications, the A25/AX25 for Linux-based applications and the 32-bit N22, the smallest in the family for deeply embedded protocol processing and entry-level MCU applications. Based on AndeStar™ V5 ISA and Andes’ industry-recognized IP quality, these products have gained widespread attention thanks to their competitive performance, power, area, and RISC-V compliance. Andes also offers SoC platforms that contain the CPU core pre-integrated with the bus matrix and rich peripheral IP for these products. The platforms enable designers to jump start their SoC designs and ease migration and integration.
To ensure the Andes V5 cores achieve their fullest performance, Andes also provides its highly-optimized compiler and production proven feature-rich IDE (integrated developer environment) to help customers achieve competitive advantage for their end products in the shortest time. Andes also provides its powerful Andes Custom Extension™ (ACE) tool COPILOT. The powerful features in COPILOT allows SoC design engineers, not familiar with processor design, to easily add customized instructions quickly to Andes processors to improve performance dramatically. Andes will release new product lines to address a wider range of applications and to continue its commitment to professional technical support to help customers create the most competitive products in the shortest time.
The AndesCore™ based on RISC-V ISA has been widely adopted by customers in Taiwan, China, Korea, Japan and the US. Through the end of 2018, 21 licensee agreements have been signed, nearly half of which were targeting artificial intelligence design. Andes Technology will continue to expand its alliance with high-quality design service providers to provide end customers faster time-to-market.