December 18, 2002 - A unique new co-processor that will result in simpler and cheaper electronic circuit board design has been launched by QinetiQ, Europe's largest science and technology solutions provider. The floating point co-processor unit (FPU) is compatible with both the Microblaze™ and PowerPC microprocessors in Xilinx field programmable gate array (FPGA) cores and eliminates the need for stand-alone floating point processors. This in turn reduces chip count, simplifies board design and reduces board size, leading to lower design and manufacturing costs.
Currently FPGA designers and users wanting the greater numerical precision provided by floating point arithmetic have to rely on additional devices and this incurs extra costs. Alternatively, engineers can use software emulation for floating point calculations but this results in reduced performance. The Quixilica® FPU, the most recent addition to QinetiQ's Quixilica® range of field programmable gate array (FPGA) cores, overcomes these problems.
By using the Quixilica® FPU in their design, FPGA engineers can cut both design time and cost without any loss of performance. For example, when combined with the Microblaze™ microprocessor, the Quixilica® co-processor produces performance of 50 MFLOPS (million floating point operations per second). An updated version of the GNU C compiler has been developed by NA Software Ltd, which allows application software to target the FPU directly. A library of optimised vector processing functions has also been developed by NA Software.
The FPU is based upon the Quixilica® library of highly optimised, pipelined, variable wordlength floating point operators. This can be used by customers who require very high performance floating point arithmetic, for example, for front-end digital signal processing (DSP), or for numerically intensive applications such as computational fluid dynamics. The library is compatible with the IEEE-754 standard and has been used to develop solutions with over 20GFLOPS (giga floating point operations per second) of sustained performance from a single FPGA.
Commenting on the launch of the Quixilica® FPU, Bill Smith, manager of QinetiQ's Real-Time Systems Laboratory, said: "The FPU is ideal for applications requiring a mix of fixed-point-intensive digital signal processing (DSP), with some floating point data processing. We're already seeing applications in image and signal processing systems, control, and support of legacy hardware, where the combination of an FPGA with an embedded microprocessor core and the FPU can provide the functionality and performance of an entire DSP subsystem."
The Quixilica® FPU enhances the standard Xilinx MicroBlaze™ or PowerPC processor by providing an IEEE-754-compliant single precision floating-point capability in hardware. The standard MicroBlaze™ C Compiler has been enhanced to automatically target the FPU from standard C code. This has been shown to accelerate floating point-intensive functions by over 35x after recompilation of the source. Significant further performance increase is possible through manual optimisation of the code and by use of a library of optimised vector processing functions.
The Quixilica® floating point arithmetic library contains fully pipelined cores that implement the arithmetic operations add/subtract, multiply, divide and square root. The library is compatible with the IEEE-754 standard, but in addition, the cores are parameterised in terms of wordlength, allowing the FPGA resource usage to be optimised for the particular application. This library has been used to develop solutions with in excess 20GFLOPS of sustained performance from a single FPGA.
QinetiQ's Real-Time Systems Laboratory currently consists of a team of 18 engineers, planning to grow to 30 over 3 years. Its mission is to fuse conventional processor technology with emerging fine-grain reconfigurable technologies to deliver high-performance signal and image processing components and systems to commercial and military markets. Specific developments include cores for digital receivers, very-high performance FFTs, floating point on FPGA and matrix inversion, and high performance adaptive beamforming and pattern recognition systems.