The 9th generation TCP-Core Accelerates an unprecedented number of 1K TCP & UDP Sessions in 100 nanoseconds with 95% TCP throughput, providing up to 8x advantage over the legacy Software-TCP-Stack.
MILPITAS, Calif., April 25, 2019 -- Intilop, Inc., a pioneer, most respected and recognized leader in providing Ultra-Low latency and Hyper-Performance Complex Networking Protocol Accelerators, Mega IP Cores, Systems and Solutions since 2009, delivers their Enhanced 10G bit 1K concurrent-TCP&UDP- Session Hardware Accelerator with Kernel-Bypass Linux driver for Altera/Xilinx FPGA boards. This 10G Hardware/Software subsystem with TCP Accelerator (TCP-Full-Offload-Engines) implements One Thousand Simultaneous TCP/UDP Connections and Bandwidth of more than 1 Gigabyte/sec per port regardless of number of simultaneous or active TCP Sessions with Kernel Bypass driver is unprecedented. An earlier version of this was demoed in SuperComputing14 in New Orleans, LA, November, 2014.
The deployment-ready, sub-system solution provides networking OEMs an Ultra-low-latency and Hyper-performance for all networking equipment segments that have to process TCP/UDP Protocol. Available in Altera/Intel and Xilinx FPGA based platforms. Now clients can accomplish this at line rate, which is much faster than processing in TCP software stack. Specifically, this TCP/UDP Accelerator is targeted towards the next generation of Cloud Computing, Data Center, Network Security, Telecomm and all other Hyper-Performance Network Computing server appliances in government and private enterprise system applications. The FPGA platform offers an 'Out of the box' working TCP hardware stacks with unprecedented functionality, ultra small core size, high performance and flexibility. The Full TCP core runs without any CPU involvement through all stages of TCP transactions, including connection set-up, data-transfer, tcp-retries and connection tear-down. The TCP connections maintain the same high throughput and low latency/processing times regardless of number of simultaneous connections in progress. This is a vast difference compared with other leading TCP Accelerator ASICs on various NICs that implement partial TCP-Offloads and suffer major performance degradation when handling just 10-20 simultaneous TCP Sessions. The unprecedented TCP throughput of more than 95% for large and small size payload data transfers on a 10G network, which is up to 8x higher as compared to TCP/IP software running on typical host CPU, which is the de-facto standard.
A special Kernel Bypass driver was developed for this platform. Clients will be able to utilize FPGAs technology from Xilinx and Altera to get all of the benefits of TCP hardware acceleration. A complete FPGA board/development Kit is delivered with pretested TOE/UOE and S/W driver subsystem, which allows customers to start using it right out of the box
Their previous 7 generations of Full TCP Accelerators provide up to 128 Simultaneous TCP Connections and have also been available on most FPGA boards/platforms.
As a pioneer, Intilop was the first company to deliver a series of Full TCP Offload Engines on FPGAs in 2009. Their sub 100 ns latency MAC+TOE&UOE are considered a 'Gold Standard' by the industry experts.
The highly deterministic performance, reliable and proven ultra-low latency, coupled with customizability offered by the 10G TOE is being effectively applied to gain wire-speed competitive edge by all Networking Equipment makers.
The Series of Cores implementing 16K, 8K, 1K, 256 and 32 Concurrent TCP Sessions is available at Xilinx: http://www.xilinx.com/products/intellectual-property/1-58SBVM.htm
Intilop is a developer, provider, a recognized leader and pioneer in advanced networking silicon IP and system solutions, custom hardware solutions, SoC/ASIC/FPGA integrator and total system solutions provider for Networking, Network Security, storage and Embedded Systems.