May 29, 2019, San Jose, California -- Google and eSilicon will present eSilicon’s journey to ASIC and IP design in the cloud
EDA in the Cloud? Yes, It’s Possible!
We often hear that the EDA industry is not yet ready for design in the cloud, usually due to objections about the nature of cloud-native technologies. However, the cloud seems like the ideal place to run chip designs: flexible compute resources available on demand, nearly infinite storage, and a pricing structure that avoids costs for idle resources. Some trailblazers in that space, like eSilicon, have realized this early on and embarked on a journey to the cloud to leverage its elasticity, performance, cost models and open the door to a new level of innovation in the EDA industry. Join us in this presentation to hear about that journey, the steps that were taken, the bumps along the road, and the building blocks that comprise this solution.
David Marshall — Enterprise Architect, Global IT, eSilicon Corp., San Jose, California
Guilhem Tesseyre — Customer Engineer Lead, Google, Inc., San Francisco, California
When & Where
Wednesday, June 5, 2019
2:00 – 2:45 PM
Las Vegas, Nevada
The Design Automation Conference (DAC 2019) is recognized as the premier conference for design and automation of electronic systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors.
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com