English
Avery Design Systems Announces SymXprop for X Accurate RTL Simulation
TEWKSBURY, MA. -- May 31, 2019 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of SymXprop that performs high accuracy semi-formal based RTL X handling to eliminate the inherent inaccuracies in logic simulators.
“Design practices involving partial reset, uninitialized memories, and clock and power gating expose SystemVerilog’s inaccurate RTL X handling semantics by creating X-optimism and X-pessimism issues in RTL simulations and result in extra engineering time needed to effectively debug and work around the issues,” said Chris Browy, VP Sales/Marketing. SymXprop analyzes X propagations in RTL simulations for combinatorial and sequential X inaccuracies using patent pending hybrid formal analysis and automatically eliminates these X inaccuracies in RTL simulations.
Highlights of the new SymXprop solution:
- Analysis modes for X-optimism and X-pessimism
- Scalable to large designs with built-in distributed parallel processing
- Analyze one or multiple submodules displaying X issues
- Supports VCS, Xcelium, and Questa simulators
Visit us at the Design Automation Conference in Las Vegas during June 2-6.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, CXL, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
|
||||||
Avery Design Systems Hot Verification IP
Related News
- Avery Design Systems Unveils SimXACT for Elimination of X Pessimism Issues in Gate-Level Simulation and Upgrades XVER X Verification
- Cadence Introduces the Spectre X Simulator, a Massively Parallel Circuit Simulator Delivering Up to 10X Faster Simulation with the Same Golden Accuracy
- Real Intent Awarded U.S. Patent for Methods and Systems for Correcting X-pessimism in Gate-level Simulation or Emulation
- Avery Design Systems Announces SimXACT 5.0 for Improved X-Verification
- Defacto Technologies Announces Synapse Design in collaboration with a major semiconductor company Reduces Simulation Time by 5X When using Defacto's RTL Design Solutions
Breaking News
- UltraSoC donates RISC-V trace implementation to enable true open-source development
- UMC Reports Sales for November 2019
- Verimatrix Completes Sale of its Silicon IP Business Unit to Rambus
- Rambus Completes Acquisition of the Verimatrix Silicon IP, Secure Protocols and Provisioning Business
- Tech Industry Heavyweight Joins SiFive - Manoj Gujral Tapped As SVP & GM of Silicon Business Unit
Most Popular
- SiFive To Present New Technologies At RISC-V Summit 2019
- Lift off: De-RISC to create first RISC-V, fully European platform for space
- Andes Presents Ground-Breaking 27-Series Processor at RISC-V Summit 2019
- New Vidatronic CTO to Innovate and Scale Technology
- Andes 45-Series Expands RISC-V High-end Processors 8-Stage Superscalar Processor Balances High Performance, Power Efficiency, and Real-time Determinism with Rich RISC-V Ecosystem
|
E-mail This Article | 
|
|
Printer-Friendly Page |