English
Avery Design Systems Announces SimCluster GLS to Accelerate Gate-Level Sign-Off Simulations
TEWKSBURY, MA. -- May 30, 2019 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of SimCluster GLS that performs gate-level parallel simulation to achieve 3-5X speed up of sign-off simulations.
“As chips get larger the feasibility of performing post-layout SDF-based gate-level simulation gets harder and harder,” said Chris Browy, VP Sales/Marketing. SimCluster GLS performs scalable parallel simulation using VCS, Xcelium, or Questa in either multi-core and datacenter cluster compute environments to simulate faster and shrink turn-around times on sign-off simulations.
Highlights of the new SimCluster GLS solution:
- No design changes, no testbench changes, no SDF changes
- Engines run with cycle-based or lock-step synchronization
- Supports all three major simulators (Xcelium/VCS/Questa)
- Simulation analyzer tool generates design block workload, port change activities, interconnect complexity between blocks, synchronization analysis, and design hierarchy report
- Automatic coarse-grained partitioning of flat and hierarchical netlists
- Patent pending methods further optimize performance
Visit us at the Design Automation Conference in Las Vegas during June 2-6.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, CXL, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
|
||||||
Avery Design Systems Hot Verification IP
Related News
- DeFacTo Unveils New Design for Test Product that Eliminates Need for Gate-level Scan; Creates Industry's First High-level DFT Sign-off Methodology
- Avery Design Systems Unveils SimXACT for Elimination of X Pessimism Issues in Gate-Level Simulation and Upgrades XVER X Verification
- Mobiveil and Avery Design Systems Extend Partnership to Accelerate Design and Verification of NVMe 2.0-Enabled SSD Development
- Real Intent Joins DARPA Toolbox Initiative to Provide Mil/Aero/Defense Grade Static Sign-Off
- Cadence Expands Collaboration with TSMC and Microsoft to Accelerate Timing Signoff for Giga-Scale Designs on the Cloud
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
|
E-mail This Article | 
|
|
Printer-Friendly Page |