Astera Labs Verifies Its System-Aware PCI Express 5.0 Smart Retimer Using Avery Design Systems PCIe 5.0 Verification IP
TEWKSBURY, Mass.-- June 18, 2019 -- Avery Design Systems, leader in functional verification solutions today announced that Astera Labs successfully utilized Avery's Peripheral Component Interconnect PCI Express® (PCIe®) 5.0 Verification IP and services to verify its breakthrough system-aware PCIe 5.0 Smart Retimer.
The Avery PCIe 5.0 VIP supports models and testsuites for the newly ratified PCI 5.0 specification including latest enhancements for retimers operating at 32 GT/s and the alternate protocol mode of operation.
“At Astera Labs, our priority is to deliver Smart Retimer products that fully meet PCIe specification and achieve plug-and-play interoperation,” said Jitendra Mohan, chief executive officer at Astera Labs. “Avery PCIe 5.0 VIP is a critical tool in our verification environment to thoroughly test our design and deliver a high quality product to our customers.”
“The PCIe 5.0 specification delivers unprecedented performance levels at 32 GT/s while extending reach of I/O system topologies and breadth of solutions spanning HPC to mobile/IoT applications,” said Al Yanes, PCI-SIG chairman and president. “The PCIe verification ecosystem space is so crucial to our members, as it helps them to develop chips and systems with highest quality, interoperability, and compliance.
About PCI-SIG
PCI-SIG is the consortium that owns and manages PCI specifications as open industry standards. The organization defines industry standard I/O (input/output) specifications consistent with the needs of its members. Currently, PCI-SIG is comprised of over 800 industry-leading member companies. To join PCI-SIG, and for a list of the Board of Directors, visit www.pcisig.com.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, CXL, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
|
Avery Design Systems Hot Verification IP
Related News
- eInfochips provides SOC engineering services to Astera Labs in developing industry's first PCIe 4.0 & 5.0 Smart Retimer SoC.
- Synopsys Design and Verification Solutions Enable Astera Labs to Develop Industry's First PCIe 5.0 Retimer SoC
- Astera Labs and Avery Design Partner on CXL 2.0 Verification for Smart Retimer Portfolio to Improve Performance in Data-Centric Applications
- Astera Labs Accelerates PCI Express 5.0 System Deployment in Collaboration with Intel and Synopsys
- Avery Design Systems Fast Tracks PCI Express 5.0 VIP
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024
E-mail This Article | Printer-Friendly Page |