SAN JOSE, Calif. July 1, 2019 -- PLDA, the industry leader in high speed interconnect solutions, today announced that it has reached a key milestone in the development of its Gen-Z silicon IP. Gen-Z is a memory-semantic fabric that eliminates existing system bottlenecks and significantly improves system efficiency and performance by unifying the communication paths and simplifying software by using the CPU-memory load/store language everywhere. Gen-Z technology is seeing increasing traction in the race to deploy high-performance disaggregated and composable IT infrastructures.
In support of immediate Gen-Z development, PLDA has released a detailed datasheet enabling designers to begin architecting and designing Gen-Z enabled SoCs. This PLDA Gen-Z IP datasheet includes the key information required for initial design including supporting features, interface description and micro architecture, gate count, performance metrics, and more.
About PLDA Gen-Z IP: PLDA’s Gen-Z IP allows host-side and media-side implementation, thanks to a flexible architecture. Key features of the PLDA Gen-Z IP include:
According to Arnaud Schleich, CEO of PLDA “PLDA strives to deliver the best and most current technologies to our valued customer base. The addition of Gen-Z to our IP product line ensures that we continue to lead the way in supporting early technology adopters.”
Kurtis Bowman, President of the Gen-Z Consortium stated: “Early IP development from leading companies like PLDA create a significant advantage for the timely implementation of Gen-Z technology into silicon developers' offerings.” Bowman adds, “We are proud to have development partners like PLDA in our ecosystem.”
More information:
You can access more information on PLDA’s Gen-Z IP as follows: