400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Cadence Appoints Jan Willis Vice President of Strategic Third Party Programs; Willis to Lead Partnership Programs with EDA, IP, and Manufacturing Communities
San Jose, Calif., January 16, 2003 - Cadence Design Systems, Inc. (NYSE:CDN) today announced it has appointed Jan Willis vice president of Strategic Third Party Programs. Willis previously was vice president of DFM Third Party Programs at Cadence.
"Jan brings the expertise and leadership to optimize the design chain for our customers through world class relationships and partnerships," said Penny Herscher, executive vice president and chief marketing officer of Cadence. The appointment is a key element of Cadence's strategy to provide a complete solution to its electronic design customers. Willis is responsible for the company's role in the Open Access consortium, its partnerships with semiconductor manufacturers and IP vendors, its cooperative efforts with more than 120 companies in the Connections(R) program, and its relationships with foundries. Willis will report to Herscher.
Prior to Cadence, Willis was vice president of Business Development at Simplex Solutions, Inc. Before joining Simplex, she served as director of Product Marketing and the Semiconductor Vendor Program at Synopsys, Inc. Earlier, Willis held engineering and marketing positions at Hewlett-Packard Company.
Willis received a master's degree in business administration from Stanford and a bachelor's degree from the University of Missouri-Columbia, where she studied electrical engineering.
About Cadence
Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,200 employees and 2002 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services are available at www.cadence.com.
Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc.
|
Cadence Design Foundry Hot IP
Related News
- Artisan Appoints New Sales Vice President; R. Keith Hopkins To Lead Artisan's North America and Europe Sales Organizations
- MosChip Technologies Appoints Semiconductor Industry Veteran, DVR Murthy As "Vice President of Strategic Initiatives" to Implement and Execute Expanded Solution Offerings
- Jennic opens third international sales office and appoints John Morris as vice president - Americas
- Monolithic System Technology, Inc. Strengthens Executive Team; Appoints Karen Lamar as Vice President of Sales and Marketing
- Breker Verification Systems Appoints Andy Stein Vice President of Worldwide Sales as Company Scales New Business Opportunities
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
- Efinix Rolls Out Line of FPGAs to Accelerate and Adapt Automotive Designs and Applications
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024
E-mail This Article | Printer-Friendly Page |