Avery Design Introduces CXL VIP
Tewksbury, MA., September 23, 2019 — Avery Design Systems, leader in functional verification solutions today announced CXL VIP supporting the latest CXL Specification 1.1 from the Compute Express Link (CXL) open standard.
“Built upon our well-established PCI Express® (PCIe®) verification IP infrastructure, the CXL supports PCIe 5.0 physical and electrical interface (PIPE 5.1) to provide advanced protocols for high-speed CPU interconnects for I/O (CXL.io), CPU-to-Memory (CXL.mem), and Cache interface (CXL.cache)”, said Chris Browy, VP Sales and Marketing of Avery Design.
Related |
CXL VIP |
The CXL VIP supports SystemVerilog/UVM host, device, PHY, and PIPE-to-PIPE box agents and models, extensive protocol checking, functional coverage, and a testsuite to ensure compliance. Common BFM features:
- Support PCIe Gen5 with alternate protocol negotiation to CXL
- Support pure PCIe mode and CXL mode for CXL.IO, CXL.Mem and CXL.Cache traffic.
- Unified user application data class for both pure PCIe and CXL traffic.
- Realistic traffic arbitration among CXL.IO, CXL.Cache, CXL.Mem and CXL control packets.
- Highly randomized and configurable
- Provides various callbacks and simplified APIs for tests writing
- Protocol analyzer debugging trace files
- User customizable way of FLIT packing
- Support full cache coherent load/store operations
- Support automatic credit-based CXL data flow control
- Supports CXL virtual LSM state machines
- Supports CXL link layer retry
- Supports CXL power management
- Support CXL reset mechanisms
Host BFM Features
- Automatic bus enumeration and configuration of the CXL hierarchies
- Support memory mapped registers (RCRB and MEMBAR0 region)
- Contains home agent with snooper filter of unlimited size
- Host memory of unlimited size
Device BFM features
- Host-managed device memory of unlimited size
- Configured as Type1, Type2 and Type3 device
|
Avery Design Systems Hot Verification IP
Related News
- Avery Design Announces CXL 2.0 VIP
- Siemens introduces Questa Verification IP solution support for the new CXL 3.0 protocol
- Cadence Accelerates Hyperscale SoC Design with Industry's First Verification IP and System VIP for CXL 3.0
- Avery Design Announces CXL 3.0 VIP
- Avery Design Systems Verification IP Helps Solid State Storage Controller Startup Validate its Designs and Get to Market Faster
Breaking News
- After TSMC fab in Japan, advanced packaging facility is next
- A System On Module (SoM) developed by Electra IC: BitFlex-SPB-A7 FPGA SoM
- Weebit Nano to demo its ReRAM technology on GlobalFoundries' 22FDX® platform
- SoC Secure Boot Hardware Engine IP Core Now Available from CAST
- QuickLogic and Zero-Error Systems Partner to Deliver Radiation-Tolerant eFPGA IP for Commercial Space Applications
Most Popular
- Former Moortec executives create chip monitor startup
- PrimisAI Unveils Premium Version of RapidGPT, Redefining Hardware Engineering
- Arteris Expands Ncore Cache Coherent Interconnect IP To Accelerate Leading-Edge Electronics Designs
- Arm Announces New Automotive Technologies to Accelerate Development of AI-enabled Vehicles by up to Two Years
- Arm's Broadest Ever Automotive Enhanced IP Portfolio Designed for the Future of Computing in Vehicles
E-mail This Article | Printer-Friendly Page |