Tewksbury, MA., September 23, 2019 — Avery Design Systems, leader in functional verification solutions today announced CXL VIP supporting the latest CXL Specification 1.1 from the Compute Express Link (CXL) open standard.
“Built upon our well-established PCI Express® (PCIe®) verification IP infrastructure, the CXL supports PCIe 5.0 physical and electrical interface (PIPE 5.1) to provide advanced protocols for high-speed CPU interconnects for I/O (CXL.io), CPU-to-Memory (CXL.mem), and Cache interface (CXL.cache)”, said Chris Browy, VP Sales and Marketing of Avery Design.
The CXL VIP supports SystemVerilog/UVM host, device, PHY, and PIPE-to-PIPE box agents and models, extensive protocol checking, functional coverage, and a testsuite to ensure compliance. Common BFM features:
CXL IP CoresCXL Verification IPs - Support PCIe Gen5 with alternate protocol negotiation to CXL
- Support pure PCIe mode and CXL mode for CXL.IO, CXL.Mem and CXL.Cache traffic.
- Unified user application data class for both pure PCIe and CXL traffic.
- Realistic traffic arbitration among CXL.IO, CXL.Cache, CXL.Mem and CXL control packets.
- Highly randomized and configurable
- Provides various callbacks and simplified APIs for tests writing
- Protocol analyzer debugging trace files
- User customizable way of FLIT packing
- Support full cache coherent load/store operations
- Support automatic credit-based CXL data flow control
- Supports CXL virtual LSM state machines
- Supports CXL link layer retry
- Supports CXL power management
- Support CXL reset mechanisms
Host BFM Features
- Automatic bus enumeration and configuration of the CXL hierarchies
- Support memory mapped registers (RCRB and MEMBAR0 region)
- Contains home agent with snooper filter of unlimited size
- Host memory of unlimited size
Device BFM features
- Host-managed device memory of unlimited size
- Configured as Type1, Type2 and Type3 device
