Third-Party Silicon and Software IP Reduces Cost and Speeds Time to Market
SAN JOSE, Calif., January 20, 2003 -- Toshiba America Electronic Components, Inc. (TAEC)* today announced the launch of the ASIC IP Partner Program and disclosed the first companies who have agreed to participate in the new program.
"The ASIC IP Partner Program is intended to provide TAEC's ASIC/SOC customers with a wide-ranging portfolio of silicon and software intellectual property (IP) to help them get to market quickly," said Richard Tobias, vice president of the ASIC and Foundry Business Unit at TAEC. He said that partners will provide ready-to-use, properly verified best-in-class IP and share TAEC's commitment to reduce time to market, minimize design risk and lower cost for its customers. The program offering encompasses Function IP, Platform IP and Advanced Platform IP.
The companies named below, who have agreed to participate in the program, are all industry leaders in their areas of expertise:
- Denali Software, Inc. (Palo Alto, Calif.), the industry leader in semiconductor IP and EDA tools for memory system design and verification, is providing its Databahn memory controller IP cores.
- GDA Technologies, Inc. (San Jose, Calif.), a leading design services and IP company specializing in embedded networking and consumer electronic designs, is providing IP cores for advanced, high-speed interconnects.
- Mentor Graphics Corporation (Wilsonville, Ore.), a world leader in electronic hardware and software design solutions, is supplying a portfolio of standards-based IP cores.
- Sonics, Inc. (Mountain View, Calif.), a semiconductor IP company focused on SOC interconnect solutions, is supplying a system-level SMART interconnect that supports multiple RISC and DSP cores.
- Synopsys, Inc. (Mountain View, Calif.), a leading supplier of connectivity IP (e.g., USB, PCI, PCI-X, Ethernet) is providing DesignWare Cores.
TAEC imposes stringent requirements for quality, test coverage, documentation and support for all selected IP, and will manage the IP vendor interface for TAEC's customers. Once those requirements are satisfied, best-of-breed silicon or software IP components will be imported to TAEC's SoCMosaic platform-based design system. TAEC's world-class ASIC engineering team will then complete the system design needed to integrate the IP into the customer's design. When the IP is ready for use, it is added to the IP Bank, an IP management system that assures consistency. Banked IP components can be used quickly and easily in any ASIC/SOC design.
TAEC's ASIC IP program roadmap includes the planned addition of digital signal processing and general purpose IP for networking, multimedia, printers and storage applications.
Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes semiconductors, flash memory-based storage solutions, optical communication devices, displays and rechargeable batteries for the computing, wireless, networking, automotive and digital consumer markets.
TAEC is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba, the second largest semiconductor company worldwide in terms of global sales for the year 2001 according to Gartner/Dataquest's Worldwide Semiconductor Market Share Ranking. Toshiba is a world leader in high-technology products with more than 300 major subsidiaries and affiliates worldwide. For additional company and product information, please visit TAEC's website at chips.toshiba.com. For technical inquiries, please e-mail Tech.Questions@taec.toshiba.com.
Toshiba America Electronic Components, Inc. ASIC IP Partner Program Quote Sheet
"Our Databahn customers have had great success in working with Toshiba's ASIC and Foundry services. Toshiba's SoCMosaic program is addressing a critical need for silicon-proven IP that reduces risk and time-to-market for chip designers. We are very pleased to offer our Databahn memory controller IP through this new program, and we look forward to more successful chip designs with our joint customers." -- Kevin Silver, vice president of marketing, Denali Software Inc.
"We are very pleased to be a charter member of Toshiba's ASIC IP Partner program. Toshiba's family of high-speed I/O PHYs combined with our line of communications link IP cores, such as HyperTransport and SPI-4, are a compelling solution. Our broad range of design services and skills will be available to Toshiba's customer base to help them get to market quickly with complex communications solutions. We look forward to working closely with Toshiba." -- Prakash Bare, vice president, IP Division, GDA Technology Inc.
"Our IP cores have undergone thorough compliance testing and are proven to work in silicon, making our broad portfolio of standards-based IP flexible and easy to integrate for a variety of applications. We strive to deliver quality IP solutions that reduce the risk of failure due to incorrect interpretation of industry standards, and take pride in Toshiba's selection of our IP cores." - Mike Kaskowitz, general manager, IP Division, Mentor Graphics Inc.
"Toshiba is one of the world's top semiconductor manufacturers, and we are very pleased that they have chosen our SMART Interconnect IP for their SoCMosaic program. SMART Interconnect IP replaces the complex mix of buses, custom interconnect and control wires typically used in SoCs with an elegant communications solution engineered to meet each core's unique performance and quality of service requirements. Our SOCCreator development environment enables Toshiba to dramatically cut RTL development time for complex SoCs that combine IP blocks from many different vendors, without compromising system performance." -- Grant Pierce, president and CEO, Sonics Inc.
"DesignWare connectivity cores have been production-proven in hundreds of products, and will now accelerate SoC development for Toshiba's ASIC and foundry service customers through the SoCMosaic program. We believe partnerships like this will encourage new SoC designs by reducing the risk of deploying a variety of IP in a system on a chip." -- John Chilton, senior vice president & general manager, IP and Design Services Business Group, Synopsys, Inc.