New Platform Reduces Time-to-Market for Customizable SOCs to 6 Months
SAN JOSE, Calif., January 20, 2003 -- Toshiba America Electronic Components, Inc. (TAEC)* today announced the introduction of SoCMosaic™ custom chip, a new platform-based design approach that can reduce time-to-market for a customizable system-on-a-chip (SOC) to as little as six months. In a companion news release also issued today, TAEC announced the ASIC IP Partner Program and disclosed the first participating companies.
SoCMosaic custom chip achieves rapid customization of complex SOC designs by using commodity IP blocks, standardized bus interfaces, a scalable bus system, a register-transfer level (RTL) testbench and high-level, cycle-accurate C simulation. Pre-verified, pre-tested commodity and differentiating IP allows maximum flexibility.
"By using a configurable IP platform, pre-verified and pre-tested IP and support for common bus interfaces, SoCMosaic custom chip can slash total design time from a typical 18 months to as little as four months," said Richard Tobias, vice president of the ASIC and Foundry Business Unit at TAEC. The turnaround time to get a finished chip to market runs about six months. "Our value proposition includes complete system level support together with Toshiba's proven high-yield, high-volume advanced process technology. For platform-based SOCs to become pervasive, ASIC vendors must take responsibility for hardware/software integration and we intend to apply our leadership." System level support includes hardware and software design (with firmware and middleware) running on cycle-accurate system-level models for early development of application software. TAEC intends to be active partners with its customers at the system design level, engaging with them early in the design process and delivering software and silicon with an innovative business model.
Mr. Tobias said that he was targeting system companies developing board-level products that were looking to add features to their end-products to increase market share or reduce system cost through SOC integration. He explained that many of those companies lacked internal design resources or the specialized skill sets needed for complex SOC design. Likely customers also include system companies temporarily without the means to do yet another chip design project.
The SoCMosaic custom chip IP platform supports standard operating systems such as Linux and other real-time operating systems, contains common peripheral functions as commodity IP blocks, including I/O, interrupts, counters and serial ports plus processor cores. Customers then select differentiating IP such as embedded DRAM, and higher level system interfaces like Ethernet, USB, 1394, PCI controllers, SerDes and optimized hardware/software application function such as VoIP, MPEG and 802.11 from Toshiba's IP library. Toshiba also offers a range of analog IP with several variants to each IP block to meet various design requirements, such as high-speed, low-power, small area or low noise.
Toshiba helps the customer implement the product by mapping a functional simulation to the platform, selecting IP from the IP library or obtaining working, verified IP blocks from third-parties. Then Toshiba engineers create a testbench to make fast, executable C models of programmable blocks for early software development. Toshiba's software services team works concurrently with hardware development for software driver and API adaptation, RTOS implementation and standardized middleware solutions. On-chip specialized hardware supports software debugging. The resulting hardware/software working model allows the design to be validated and tested before implementation.
Over the course of the next year, TAEC is planning to roll out the following with prioritization based upon customer demand:
- An FPGA board to implement the platform with customer IP extensions. This is useful for software validation and hardware environment testing.
- A second platform that adds DSP to get a RISC/DSP/logic pre-verified multi-master starting point for derivatives design.
- Software service with API adaptation and RTOS implementation. The inclusion of standardized middleware is possible (i.e., MPEG4, JPEG, MP3, etc.)
- An expanded IP library targeting general purpose IP for networking, multimedia, printer and storage applications.
- High-level C models for functional execution of the design before implementation and early software development before the hardware is ready.
- Platforms are provided as soft RTL code that is synthesizable into any technology, including 0.18-micron, 0.13-micron, 90 nanometer (nm) or 65nm. Speed optimization services will be provided by Toshiba.
Availability and Pricing
TAEC is accepting a limited number of designs now and expects to announce general availability of the first SoCMosaic custom chip platform in April 2003. The V.1 platform is aimed at embedded applications that will combine application-specific support with a single control processor running Linux or an RTOS in low-end networking and consumer applications. Customer sample shipments are expected to begin the second quarter of 2003. SoCMosaic custom chip platform V.2 will add support for multiple processor cores and high-throughput multimedia and high-end networking systems. V.2 is in development with availability expected the second half of 2003.
SoCMosaic custom chips differ in complexity and include both software and silicon deliverables. Non-recurring engineering costs vary widely.
SoCMosaic Building Blocks
|Platform Name ||SoCMosaic Custom Chip V1.0 |
|Process ||0.18-micron , 130nm and 90nm |
|ASIC Capability ||TC260, TC280 and TC300 ASIC capability: tools, libraries, cells, embedded DRAM, IP cores |
|Processor ||ARM family of CPUs and AMBA peripherals |
Board support kits for Linux as RTOS (VxWorks and Nucleus on demand)
|Memory Controllers ||Denali Databahn memory controllers |
|Standard Interfaces ||PCI, Ethernet, USB (including drivers), HyperTransport SPI-4 |
|IP Libraries ||ARM, Mentor and Synopsys |
|System Bus ||Sonics system-level bus, OCP |
Supports multiple RISC and DSP cores
|System Level Support ||Platform kernel and development environment for system-level verification and SoCMosaic bring-up |
SystemC models, FPGA breadboard, Platform development system
|SoCMosaic Starter Kit ||Platform IC, software kit, migration kit from board to SoCMosaic |
Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes semiconductors, flash memory-based storage solutions, optical communication devices, displays and rechargeable batteries for the computing, wireless, networking, automotive and digital consumer markets.
TAEC is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba, the second largest semiconductor company worldwide in terms of global sales for the year 2001 according to Gartner/Dataquest's Worldwide Semiconductor Market Share Ranking. Toshiba is a world leader in high-technology products with more than 300 major subsidiaries and affiliates worldwide. For additional company and product information, please visit TAEC's website at chips.toshiba.com. For technical inquiries, please e-mail Tech.Questions@taec.toshiba.com.