Company Continues to Execute on High-Yield, High-Volume Production Strategy
SAN JOSE, Calif., January 13, 2003 -- Toshiba America Electronic Components, Inc. (TAEC)* today detailed its advanced system-on-a-chip (SOC) strategy and announced the launch of its new 90 nanometer (nm) TC300 family based on the Toshiba Corporation (Toshiba) complementary metal oxide semiconductor (CMOS) process, CMOS4. Employing 11-layers of copper wire and low-k insulating material, TC300 delivers roughly a 100 percent increase in gate integration, a 20 percent increase in gate speed and a 50 percent reduction in power consumption, compared to the previous generation 0.13-micron process technology (TC280). Toshiba is now accepting designs with several designs in development. The first customer samples have already been shipped.
According to Richard Tobias, vice president of the ASIC and Foundry Business Unit at TAEC, "Toshiba is the recognized industry leader in advanced process technology and our 90nm process leverages the experience gained with our 0.13-micron-generation SOCs." Unlike its competitors, Toshiba implemented a deliberate low-risk 0.13-micron production strategy of putting an aluminum interconnect version into production first and following with a copper interconnect version afterwards. "As a result of our high-yield, high-volume approach," Mr. Tobias continued, "our 0.13-micron SOCs have been in production since October 2001 and we are currently shipping high-volume production quantities. Having already shipped our first TC300 customer samples, we are on course with our new 90nm technology."
The CMOS4 build-on-modular process permits easy mixing of mixed signal, dynamic random access memory (DRAM) and application specific intellectual property (IP) on the same chip. TC300 is targeted at next-generation, high-end applications ranging from high-speed intensive networking and server applications to digital multimedia devices that manage audio/video information and portable wireless devices that require low-power consumption.
TC300 features two types of embedded DRAM optimized for speed or density. Mr. Tobias said, "Toshiba is currently the only company with 90nm embedded DRAM suitable for mass production."
Key features of the TC300 are as follows:
- The process supports up to 11 layers of copper metal interconnect with low-k dielectric and logic densities up to 400,000 gates/mm2.
- The cell libraries encompass a vast portfolio of compact, primitive cells optimized for automatic synthesis and multi-threshold voltage. This makes it possible to select fast, ultra-fast or low-power consumption cells for the optimal design results.
- Input/output (I/O) cells support high-performance serializer/deserializer (SerDes) chip-to-chip interface applications for backplane and line card products as well as GigaEther, FibreChannel, Sonet and Wi-Fi (IEEE1394b) applications.
- Static random access memory (SRAM) cores support fast SRAM, high-integration SRAM, register files and high-integration read only memory.
- The embedded DRAM employs Toshiba's unrivaled trench capacitor technology that permits mixing of logic and DRAM processes without degrading performance. Two kinds of DRAM cores are available:
- The SD type DRAM for high-bandwidth applications has a clock cycle of 300 megahertz (MHz) maximum and a data transfer rate of 9.6 gigabytes per second (GPS) maximum.
- The FA type DRAM is optimized for fast access with a random access time range of 6-8 nanoseconds (ns) and an I/O width of 288 bits maximum.
- A rapidly growing library of application specific IP includes processor cores, memory, analog functions and networking IP.
- The process has three sets of Vth transistors available; gates can be optimized for performance and/or power. These three sets are:
- Low Power = 0.4 Volt (V)
- High Speed = 0.3V
- Very High Speed = 0.2V
- There are two options for I/O slots:
- Standard, which is suitable for most designs
- Low height for pad-limited designs.
- A range of package types for high-performance SOCs are available, including 200-2,304 pin flip chip ball grid array (FCBGA), 109-256 PFBGA chip scale package and a 256-868 pin PBGA package with a multi-layer structure and superior electrical characteristics. TAEC also expects that this technology will be used for large chips incorporated with smaller mixed signal chips in small outline package (SOP) solutions.
Toshiba has developed a new, advanced EDA methodology for the TC300. The sign-off interface uses the industry-standard Synopsys static timing analysis (STA) and standard test interface language (STIL.) These new interfaces allow greater timing precision and make it easier for fabless semiconductor companies to interface with Toshiba. In addition, TC300 is supported by full-chip hierarchical design implementation and verification methodologies. Toshiba has also added enhanced signal integrity and cross talk analysis tools. This design environment supports virtually all of the industry's leading-edge tools, including the Cadence and Magma design environments.
Availability and Future Plans
TC300 is now available for immediate design acceptance and the first customer samples have already been shipped. TC300 is slated to begin ramping for mass production in the second quarter of 2003 with high-volume production expected in the third quarter of 2003.
Technical Specification Summary
|Product Name ||TC300 |
|Process ||CMOS4 90nm (gate length: 70nm) low-k dielectric process |
|Metal Wire ||11 layers of copper metal interconnect |
|Internal Power Supply Voltage ||1.2V ± 0.1V |
|Input/Output Voltage ||2.5V, 3.3V, or 1.8V (optional) |
|Gate Density ||400,000 gates/mm2 or more |
|Gate Delay || |
Very high speed type: 9.5 picoseconds(ps)
High speed type: 11ps
Low-power type: 14ps (fanout = 1, CIV x 4 cells)
|Power Consumption ||7nW/MHz/Gate (CIV x 1 cell) |
|DRAM Core ||4-32 megabits per block at 64/128/256 bits wide |
Typically two to four cores per design
|SD Type DRAM || |
Clock Cycle: 300MHz maximum
Data Transfer Rate: 9.6GB/sec.
I/O Width: 256 bits maximum
Bit Scale: 4-32Mb/Block
|FA Type DRAM || |
Random Access Time: 6-8ns
I/O Width: 288 bits maximum
Bit Scale: 4-9Mb/Block
Building on Proven Process Leadership
Toshiba is the recognized industry leader in advanced process technology designed for manufacturability and upholds a multi-generation track record for reliability, cost-effectiveness and fast ramp-up to high-volume production. With five generations of embedded DRAM manufacturing under its belt, Toshiba has supplied more embedded DRAM parts than any other company in the world. Based on this process core competency, several of the world's leading companies have chosen to team up with Toshiba on next-generation silicon technology for the SOC era. The leading-edge 90nm CMOS4 silicon technology was jointly developed by Toshiba Corporation and Sony Corporation. The two companies are also working on 65nm CMOS process technology for embedded DRAMs, as announced in conjunction with IEDM last month. As well, Toshiba has an alliance with Fujitsu for SOC collaboration. In July Toshiba joined with ten other Japanese companies to form Advanced SOC Platform Corp. (ASPLA) which is establishing a standardized design and process base for 90nm technology.
Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes semiconductors, flash memory-based storage solutions, optical communication devices, displays and rechargeable batteries for the computing, wireless, networking, automotive and digital consumer markets.
TAEC is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba, the second largest semiconductor company worldwide in terms of global sales for the year 2001 according to Gartner/Dataquest's Worldwide Semiconductor Market Share Ranking. Toshiba is a world leader in high-technology products with more than 300 major subsidiaries and affiliates worldwide. For additional company and product information, please visit TAEC's website at chips.toshiba.com. For technical inquiries, please e-mail Tech.Questions@taec.toshiba.com.