- Power consumption only 20% of current low power CPLDs, ideal for battery-based products
- Family provides programmable solutions for portable and handheld electronics
HILLSBORO, OR -- January 20, 2003 - Lattice Semiconductor Corporation (NASDAQ: LSCC), the inventor of in-system programmable (ISPTM) logic products, today announced the immediate availability of the first member of its 1.8-volt ispMACH 4000Z® CPLD family that sets a new standard for the industry's lowest static power consumption. The ispMACH 4032Z device is the first of three initial ispMACH 4000Z devices which span logic capacities from 32 to 128 macrocells. These breakthrough devices provide extremely low static current consumption (20 microamps worst case for a 32 macrocell device) and cost effective logic implementation demanded by handheld and portable applications. By reducing static power consumption to only 20% of previous devices, the new family dramatically expands the application scope of programmable logic in the portable and handheld arenas and provides new programmable solutions within the $6.9 Billion portable consumer semiconductor market as well as other power-conscious segments. These ultra-low power features are also coupled with high-speed operation: the ispMACH 4032Z device provides 3.5ns pin-to-pin delay (tPD), 3.0ns clock-to-output delay (tCO), 2.2ns set-up time (tS), and 265MHz operating frequencies (fMAX).
Traditionally, requirements for low standby power and low cost have limited the use of PLDs in handheld and portable equipment. "The ispMACH 4000Z combines the industry's lowest static power with an extremely cost effective solution," said Stan Kopec, Lattice vice president of corporate marketing. "It is suitable for a wide variety of handheld, portable, and consumer products. At only one-fifth the power consumption of current low-power CPLDs, it will dramatically expand the applications that programmable logic can address within these markets." The ispMACH 4000Z is targeted for applications including cell phones and peripherals, paging devices, GPS positioning equipment, PDAs, digital still camera's, digital video camera's, personal audio equipment, portable medical equipment, automotive telematics and radio, and industrial instrumentation.
Industry's Lowest Static Power Consumption / Fastest Performance
Standby time is a key design requirement for portable and handheld equipment. Designers want to minimize the standby or static power associated with logic within their designs to maximize the interval between battery charges or replacement. In designing the ispMACH 4000Z, Lattice took its popular ispMACH 4000 architecture, re-optimized its non-volatile E2CMOS® process technology and redesigned key circuit elements to reduce static power by over a factor of 50. As a result, the maximum static current consumption for devices in the family ranges from 20 to 30 µA over the commercial operating temperature range, while still maintaining the industry's fastest performance for a low-power CPLD solution.
Power Supply and I/O Standard Support
The ispMACH 4000Z operates from a nominal 1.8-volt power supply with operation extended down to 1.5-volts, accommodating the end of battery life voltage of certain systems. The ispMACH 4000Z devices have two I/O banks, each with their own power supply voltage that can be set at the appropriate voltage to support LVTTL and LVCMOS 3.3, 2.5, and 1.8-volt outputs. The device input buffers have programmable thresholds that support the above standards independent of the I/O bank voltage. Extended range 3.3-volt I/O are supported instead of the more common narrow range version of the standard, again accommodating the end of battery life voltages associated with certain systems. The I/Os on the ispMACH 4000Z are 5-volt tolerant to also facilitate connection to legacy chips and interfaces.
All ispMACH 4000Z devices are Boundary Scan Testable and in-system programmable through an IEEE 1532-compliant JTAG boundary scan (IEEE 1149.1) interface.
The ispMACH 4000 product line is supported by Lattice's new ispLEVER TM design tools. The ispLEVER tools, Lattice's platform for next-generation logic design, provide designers with rapid access to the performance of the ispMACH 4000Z devices while maximizing resource utilization. This is achieved through timing driven placement & routing coupled with optimized synthesis support from vendors such as Exemplar and Synplicity. Additional third-party EDA tool support is provided through industry standard EDIF netlist import and export. The ispLEVER software is available in PC as well as UNIX workstation versions.
Price and Availability
The ispMACH 4032Z is available now in 48-pin TQFP and space-saving 0.8 millimeter ball pitch 49-ball chip array Ball Grid Array (caBGA) packages in commercial, industrial and automotive temperature options. These small PCB-footprint packages, with body sizes only 7 millimeters square, are supported to satisfy the tight space constraints often found with portable and handheld equipment. The ispMACH 4000Z family also supports system designers' needs for density migration within a common package/pinout footprint. ispMACH 4000Z devices are also pin-compatible with ispMACH 4000C devices in corresponding packages. The balance of the ispMACH 4000Z devices are expected to be released mid-2003. Projected pricing for the ispMACH 4032Z is less than $1.00 in 100,000 piece quantities.
About Lattice Semiconductor
Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISPTM programmable logic devices (PLDs), Field Programmable Gate Arrays (FPGAs) and Field Programmable System-on-a-Chip (FPSC) devices. Lattice offers total solutions for today's system designs by delivering the most innovative programmable silicon products that embody leading-edge system expertise.
Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268- 8000, FAX 503-268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com.
Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.
Lattice Semiconductor Corporation, L (& design), Lattice (& design), in-system programmable, ispLEVER, SuperFAST, ispMACH, E 2 CMOS, ISP and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.
GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.