SmartDV Heads to DVCon Europe to Showcase VIP Support for Verilator and TileLink, Demonstrate Smart ViPDebug Protocol Debugger
Smart ViPDebug Demo will Highlight Ability to Reduce Debug Time through Linked Waveform, Transaction Database Views
SAN JOSE, CALIF –– October 17, 2019 ––
WHO: SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP) supporting simulation, emulation, field programmable gate array (FPGA) prototyping, post-silicon validation, formal property verification, Design IP, custom VIP and Design IP development, RISC-V verification services
WHAT: Will highlight its range of VIP at DVCon Europe (Booth #404) and demonstrate its Smart ViPDebug™, a protocol debugger that reduces debug time by rapidly identifying violations. It will profile its VIP support for Verilator, the free, open-source hardware description language (HDL) simulator. Also showcased will be TileLink VIP to verify the TileLink chip-scale interconnect standard, an open-source, high-performance and scalable cache-coherent fabric for RISC-V based system on chip (SoC) designs.
WHEN: Tuesday, October 29, and Wednesday, October 30
WHERE: Holiday Inn Munich City Centre, Munich, Germany
Attendees can schedule meetings to discuss SmartDV’s support for Verilator and TileLink or arrange for private demos at demo@smart-dv.com to learn more about Smart ViPDebug.
About SmartDV
SmartDV™ Technologies is the Proven and Trusted choice for Verification and Design IP with the best customer service from more than 250 experienced ASIC and SoC design and verification engineers. Its high-quality standard or custom protocol Verification and Design IP are compatible with all verification languages, platforms and methodologies supporting all simulation, emulation, FPGA prototyping and formal verification tools used in a coverage-driven chip design verification flow. The result is Proven and Trusted Verification and Design IP used in hundreds of networking, storage, automotive, bus, MIPI and display chip projects throughout the global electronics industry. SmartDV is headquartered in Bangalore, India, with U.S. headquarters in San Jose, Calif. Visit SmartDV to learn more.
|
SmartDV Technologies Hot IP
SmartDV Technologies Hot Verification IP
Related News
- SmartDV to Demonstrate TileLink Verification IP for RISC-V Based Systems, Smart ViPDebug Protocol Debugger at DVCon India
- SmartDV's TileLink, Verilator VIP on Full Display at RISC-V Summit
- SmartDV Reduces Protocol Debug Time with Smart ViPDebug
- SmartDV Broadens Support for Arm AMBA Protocol with Verification IP Solutions for AMBA CHI, CXS, LPI
- SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator
Breaking News
- Keysight, Synopsys, and Ansys Deliver Radio Frequency Design Migration Flow to TSMC's N6RF+ Process Node
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Leveraging Cryogenics and Photonics for Quantum Computing
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
- Credo at TSMC 2024 North America Technology Symposium
Most Popular
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Alphawave Semi: FY 2023 and 2024 YTD Trading Update and Notice of Results
E-mail This Article | Printer-Friendly Page |