90nm OTP Non Volatile Memory for Standard CMOS Logic Process
Lift off: De-RISC to create first RISC-V, fully European platform for space
Launched on 1 October 2019, the European Innovation Action De-RISC is preparing a full hardware-software platform based on RISC-V for the space and aviation market.
Barcelona, 3 December 2019 – Combining a multicore system-on-chip by leading space solutions provider Cobham Gaisler with fentISS’ space-qualified XtratuM hypervisor, De-RISC will create a market-ready platform to power future space and aeronautical applications with made-in-Europe technology.
Thanks to Barcelona Supercomputing Center’s proven multicore interference mitigation techniques, the platform will offer high-performance operation with dramatically reduced interference. Meanwhile, Thales, one of the strongest players in the space and aviation market worldwide, will test the platform on real aerospace applications.
‘With the first RISC-V based, fully European platform for space, De-RISC will guarantee access to made-in-Europe technology for aerospace applications, thus contributing to the “Technologies for European non-dependence and competitiveness” programme in these strategic markets,’ said Paco Gomez Molinero, chief executive officer of fentISS and coordinator of the De-RISC project.
The use of RISC-V will also help to future-proof the platform, thanks to an ever-increasing support for the open-source instruction set architecture (ISA), at a time when the proprietary PowerPC and SPARC architectures traditionally used in aviation and space systems are experiencing a loss of momentum. As a result, the space industry is not able to leverage software from the commercial domains, fuelling a need to shift to architectures present in higher volume commercial markets. The final platform will be portable to other architectures, and it will also provide superior fault tolerance.
The four partners together represent a formidable team for computing in space. Cobham Gaisler is one of the main providers of processors for the European Space Agency (ESA), while the fentISS XtratuM hypervisor has been used in the latest generation of ”NewSpace” satellites. Barcelona Supercomputing Center (BSC) has a rich portfolio of projects developing the latest technologies for space. Meanwhile, Thales’ long experience in designing, operating and delivering satellite-based systems make them ideally placed to validate the technology for space applications.
About De-RISC
De-RISC (Dependable Real-time Infrastructure for Safety-critical Computer) is a 30-month Innovation Action partially funded by the European Commission, which was launched on 1 October 2019. With a budget of € 3,444,625, the project addresses computer systems within the space and aviation domains. It will introduce a market-ready hardware-software platform based on the RISC-V instruction set architecture (ISA), productizing a multi-core RISC-V system-on-chip designed by Cobham Gaisler and an efficient time and space partitioning based on the fentISS XtratuM hypervisor.
The project consortium comprises four partners, all of whom have extensive experience in the safety-critical and aerospace domains. The XtratuM hypervisor by fentISS (Spain) has been selected for different space missions including the OneWeb satellite constellation, the PLATINO generic satellite for constellations, ARGOS ANGELS, EyeSat, MERLIN, JUICE and MMX among others. The LEON processor series developed by Gaisler has been used in a variety of ESA missions. BSC is one of the leading research institutions in Europe and has closely collaborated with Gaisler and Thales in European projects such as SAFURE and PROXIMA. Thales is a world leader for mission critical information systems with ample experience in the aerospace, telecommunications and security domains.
|
Frontgrade Gaisler Hot IP
Related News
- De-RISC first anniversary, a H2020 project which will create the first RISC-V, fully European platform for space
- De-RISC, the H2020 project which will create the first RISC-V fully European platform for aerospace, celebrates its second anniversary
- Semidynamics and SignatureIP create a fully tested RISC-V multi-core environment and CHI interconnect
- The European Space Agency (ESA) has awarded a contract to CAES, in the frame of the ARTES Competitiveness & Growth programme, to develop System-on-Chip for space applications
- SEALSQ Introduces QS7001, a Newly Developed Cutting-Edge RISC-V Secure Hardware Platform, Specifically Designed for IoT security in the Post-Quantum Era
Breaking News
- TSMC September 2024 Revenue Report
- Crypto Quantique teams up with Attopsemi to simplify the implementation of PUF technology in MCUs and SoCs
- Intel, TSMC to detail 2nm processes at IEDM
- SensiML Expands Platform Support to Include the RISC-V Architecture
- MIPI Alliance Announces OEM, Expanded Ecosystem Support for MIPI A-PHY Automotive SerDes Specification
Most Popular
- Deeptech Keysom completes a €4M fundraising and deploys the first “no-code” tool dedicated to the design of tailor-made processors
- Bluetooth® V6.0 Channel Sounding RF Transceiver IP Core in 22nm & 40nm for ultra-low power distance aware Bluetooth connected devices
- Secure-IC unveils its Securyzr™ neo Core Platform at Embedded World North America 2024
- LDRA Announces Extended Support for RISC-V High Assurance Software Quality Tool Suite to Accelerate On-Target Testing of Critical Embedded Applications
- Electronic System Design Industry Posts $4.7 Billion in Revenue in Q2 2024, ESD Alliance Reports
E-mail This Article | Printer-Friendly Page |