Munich, Germany – December 10th, 2019 – Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, announced today that it has joined forces with Western Digital Corp. (NASDAQ: WDC) to become the preferred provider of hardware implementation packages and expert technical support for users of Western Digital’s SweRV CoreTM EH1, a RISC-V core currently available to the open-source community and further supported by the open-source development organization CHIPS Alliance. CHIPS Alliance is a barrier free environment which allows collaboration for open-source software and hardware code.
The SweRV Core EH1 is a 32-bit, 2-way superscalar, 9-stage pipeline core introduced earlier this year by Western Digital, a leader in data infrastructure. With performance of up to 4.9 CoreMark/MHz and a small footprint, it offers compelling capabilities for embedded devices supporting data-intensive edge applications, such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems. The power-efficient design also offers clock speeds of up to 1.8 GHz on a 28nm CMOS process technology.
The new SweRV Support Package (SSP) from Codasip provides all of the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip, including but not limited to verification testbenches and intellectual property, reference scripts for leading EDA flows, models for simulation and emulation, and software development tools—all backed by professional technical support.
“Codasip is delighted to partner with Western Digital to facilitate the adoption of SweRV in production silicon. The SweRV Core EH1 offers compelling performance with energy efficiency, and with our SSP, users can confidently implement the SweRV Core into their chip at a fraction of the cost of competing technologies,” said Karel Masařík, CEO of Codasip. “By offering this service, we hope to contribute significantly to companies that are turning to open IP to innovate within their next semiconductor device. Also, we plan to continue development of the SweRV Core under the CHIPS Alliance organization.”
“The SweRV Support Package from Codasip is an exceptional complement to our SweRV Core EH1, combining a production-grade core with end-to-end support tools and resources so that companies can confidently deploy a RISC-V core for their unique needs,” said Zvonimir Bandić, senior director of next generation platforms architecture at Western Digital. “By teaming up with Codasip, we make it even easier to transition to RISC-V and further expand the potential for innovation that brings computing power closer to data.”
The SweRV Core EH1 complements a full portfolio of RISC-V innovations developed and open-sourced by Western Digital as part of its commitment to advancing the RISC-V ecosystem and accelerating development of new open, purpose-built architectures. The core is available through CHIPS Alliance, a project hosted by the Linux Foundation to foster a collaborative environment to accelerate the creation and deployment of open SoCs, peripherals and software tools for use in mobile, computing, consumer electronics, and Internet of Things (IoT) applications.
The SSP, along with optional professional technical support services, will be available for licensing in Q1 2020 directly from Codasip.
Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Munich, Germany, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. For more information about our products and services, visit www.codasip.com.