0-In Announces Industry-Leading Verification Technology for Clock-Domain Crossings in SoC Devices
SAN JOSE, Calif. – January 27, 2003 – Today 0-In Design Automation, The Assertion-Based Verification Company, announced new technology to verify clock-domain crossings in complex multiple-clock ASICs and System-on-Chip (SoC) devices. This technology is available in the new 0-In Checklist product, part of 0-In's V2.0 Assertion-Based Verification (ABV) Suite. 0-In Checklist is the first to combine automatic clock-domain crossing (CDC) analysis and automatic generation of CDC monitors. (See today's release entitled "0-In Announces New Products Based on Breakthrough Formal Verification Algorithms" for product details).
The 0-In Clock-Domain Crossing Solution
0-In Checklist provides the industry's only complete clock-domain crossing (CDC) methodology, including:
- Automatic detection of signals crossing clock domains
- Static formal verification to find unsafe synchronization
- Automatic generation of synchronization monitors
- Promotion of synchronization monitors for use with simulation and formal verification
0-In Checklist analyzes all clocks within the chip, automatically detecting clock-domain crossings and checking for correct synchronization. This analysis encompasses numerous popular synchronization methods and provides the widest RTL style support of any tool in the industry.
0-In Checklist automatically creates synchronization monitors, including:
- Direct control synchronization
- Direct data synchronization
- Buffer synchronization
At the designer's option, these synchronization monitors can be added into simulations or sent to formal engines for further analysis.
SoC devices often use independent clocks to drive different blocks. For example, the processor bus, peripheral bus, memory ports and external interfaces may all operate on independent clocks. A clock-domain crossing happens when a signal clocked by a transmit clock is sampled by a register clocked by a receive clock that is asynchronous to the transmit clock. In this case, the signal may change value very close to the edge of the receive clock, causing the output of the sampling register to become metastable before it settles randomly to either the old value or the new value. If the CDC involves a multiple-bit signal, then each bit of the sampling register may independently settle to either the old or new value.
To avoid unpredictable behavior related to metastability, SoC designs must properly synchronize all control signals that cross clock domains, and they must follow proper handshaking protocol to ensure that multiple-bit signals that cross clock domains are used only when all the bits are consistent. 0-In Checklist automatically detects each clock-domain crossing, analyzes the synchronization method, and produces a monitor that checks for proper synchronization in simulation. The tool also produces a monitor that allows 0-In's formal verification tools to exhaustively verify proper synchronization. Formal verification of proper synchronization across clock domains is a unique capability of 0-In's ABV tool suite.
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution that provides value throughout the design and verification cycle – from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.
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