Accellera Forms Functional Safety Working Group to Standardize Data for Interoperability & Traceability in the Functional Safety Lifecycle
Standard will target the capture and propagation of functional safety intent across different safety operations and work products
Elk Grove, Calif., February 18, 2020 -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today the formation the Functional Safety Working Group (WG). The charter of the new working group is to create a standard that improves interoperability and traceability in the functional safety lifecycle, specifically targeting analysis, design, verification and implementation operations and related safety work products.
“We have had tremendous participation and input from the community since the formation of our proposed working group,” stated Lu Dai, Chair of Accellera. “The industry is eagerly awaiting a standard that unifies functional safety best practices into an industry-agreed methodology supported by a functional safety format. We encourage anyone interested in contributing to advancements in this area to join us and help develop and shape this important standardization initiative.”
“Our objective is to develop a standard which captures and propagates the functional safety intent. This helps to better integrate analysis methods such as FMEDA, DFA and FTA and to enable a functional safety-aware design and verification flow for electronic circuits and systems,” stated Alessandra Nardi, Functional Safety WG Chair. “Enabling functional safety is a fascinating multi-disciplinary challenge which significantly benefits from alignment and standardization across the supply chain involving different industries and domains. With safety critical applications in mind, we are truly looking forward to this collaborative effort.”
The WG will initially focus its efforts on the development of a white paper to explain the motivation and possible directions in the creation of a functional safety standard, followed by a Language Reference Manual (LRM) that will provide the definition of the functional safety format.
Background on Functional Safety Working Group
The formation of the Functional Safety WG is the follow-up of a proposed working group that assessed the need for a standardized language or format to specify functional safety information and enable interoperability.
Key industry leaders from 19 companies have already committed to join the new WG.
The Functional Safety Working Group will meet regularly via teleconferencing. The next face-to-face meeting will be held the week of March 30 in Austin, Texas. To find out more about the working group, visit the working group page. If you are not already an Accellera member and are interested in joining in order to participate in the working group, visit here.
The Functional Safety WG will hold a Birds of a Feather at DVCon U.S. on Monday, March 2 from 6:30-7:30pm in the San Jose Room. Register for the meeting here. All DVCon U.S. attendees are welcome, including those with a free Exhibits Only pass. During the BoF, the ongoing activities of the Functional Safety WG will be discussed along with a Q&A with attendees interested in joining the development of this new standard.
About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership.
|
Related News
- Accellera Systems Initiative Launches Working Group to Standardize Interoperability of Multiple Language Verification Environments and Components
- UVM-AMS Working Group Formed to Standardize UVM Analog/Mixed-Signal Extensions
- Accellera Announces Standardization Initiative to Address Design Automation and Tool Interoperability for Functional Safety
- Accellera Forms IP Security Assurance Working Group
- Accellera Systems Initiative Forms Portable Stimulus Working Group
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |