Data Demands Drive Co-Packaged Silicon and Optics for Switch Fabrics
By Nitin Dahad, EETimes
March 12, 2020
When we talk about having billions of connected devices, that also means massive growth in data, as well as data centers with increased performance and network bandwidth to process that data. Modern data center switches rely on pluggable optics installed in the switch faceplate that are connected to switch serializer/deserializer (SerDes) ports using an electrical trace.
But as data center switch bandwidth grows to meet demand, connecting the SerDes to pluggable optics electrically will become more complex and require more power. This is likely to present bandwidth scalability challenges in terms of density, cost, and power; challenges that require tighter integration of optics and networking silicon.
E-mail This Article | Printer-Friendly Page |
Related News
- Rambus Delivers 112G XSR/USR PHY on TSMC 7nm Process for Chiplets and Co-Packaged Optics in Networking and Data Center
- Innovium Adopts the Cadence Innovus Implementation System for Its Highly Scalable Switch Silicon Family for Data Centers
- Alphawave Semi Spearheads Chiplet-Based Custom Silicon for Generative AI and Data Center Workloads with Successful 3nm Tapeouts of HBM3 and UCIe IP
- Marvell Demonstrates Industry's First 3nm Data Infrastructure Silicon
- Synopsys Advances Silicon Lifecycle Management to Accelerate Data Transport and Significantly Reduce Test Time
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Intel and Arm Team Up to Power Startups
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- Renesas Introduces Industry's First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core
- SmartSoC Solutions Joins TSMC Design Center Alliance to Boost Semiconductor Innovation in India