San Jose, CA – April 3, 2020 – eInfochips (an Arrow Company), a leading global provider of product engineering and semiconductor design services, will be exhibiting at Design & Reuse IP-SoC Silicon Valley 2020 on 9th April in Mountain View, California. eInfochips’ team will be displaying their capabilities in lower geometry design, IP integration issues in terms of block to SoC level and how to achieve key PPA (Power, Performance, Area).
The event will feature an industry talk by Maulik Patel (Technical Lead), Milan Dalwadi(Technical Lead), eInfochips. The speakers will talk about how IPs (Blocks, IP, modules) are becoming an important part of the SoC design cycles and how reusability is a key factor while creating SoCs.
Most relevant question today is how we can improve the PPA using the right methodology, framework like OptiX (Automation flow) and EDA tools in the market. In this presentation we will elaborate how we successfully taped out multimillion 16nm FinFET SoC having complex blocks using our Design services capabilities. It discusses about the timing, congestion and sign-off issues and how our approach came to the rescue with its advanced features enabling us to improve the TAT by reducing the PNR/sign-off iterations.
The talk will highlight some of the implementation challenges during hardening, and the methodical approach used to converge in the solution. This will be based on the company’s experience at 16nm, 12nm, and 07nm IPs/blocks.
Featured Talk at IPSoC:
When: 9th April 2020
Detailed schedule and registration.
Topic: 300Mn gate Data Centre SoC challenges and PPA insights.
Author : Maulik Patel (Technical Lead) and Milan Dalwadi (Technical Lead), eInfochips
About eInfochips
With 25 years of experience in the Semiconductor industry, eInfochips helps its clients with custom designs of ASICs, SoCs, and FPGAs. Over these years, the company has worked catered to verticals including Aerospace, Automotive, Consumer Electronics, Industrial, IoT, Medical, and Networking among others. With strong expertise in mixed-signal solutions across physical design, verification, and validation, eInfochips specializes in lower geometry designs and has taped-out chips from 180nm to 7nm and beyond. eInfochips is the 1st engineering services company to have worked on 7nm and 10nm technology nodes.