DARPA Looks to Automate Security for IC Design
By George Leopold, EETimes (May 27, 2020)
The latest in a series of Pentagon semiconductor initiatives seeks to embed security features into chip designs that would allow silicon architects to probe economics-versus-security tradeoffs while baking in security throughout device lifecycles.
The chip design effort represents continuing U.S. efforts to secure its electronics supply chain as semiconductors emerge as a choke point in what is shaping up as a technological Cold War with China.
DARPA announced two teams this week to ramp up its year-old Automatic Implementation of Secure Silicon (AISS) program led by Synopsys and Northrop Grumman. Both teams will develop Arm-based architectures that incorporate a “security engine” used to defend against attacks and reverse-engineering of chips. An upgradeable platform would provide the infrastructure that military planners say is needed to manage hardened chips throughout their lifecycles.
Related News
- Optima Launches New IC Security Verification Solution
- FortifyIQ Sets the Stage at the Design Automation Conference for Revolutionizing Chip Design with Pre-silicon Security Verification
- Thalia's AMALIA Technology Analyzer de-risks Analog IP reuse for major IP houses and IC manufacturers
- Rambus Joins DARPA Toolbox Initiative with State-of-the-Art Security and Interface IP
- Secure-IC Announces Partnership With U.S. DARPA To Foster Security Technology Innovation
Breaking News
- GlobalFoundries and NXP to Deliver Next-Generation 22FDX Solutions for Automotive, IoT and Smart Mobile
- Celestial AI Acquires Rockley Photonics Patent Portfolio, Strengthening Photonic Fabric IP
- Silicon IP Provider, Chips&Media Unveils New Multi Video Codec IP, WAVE6 Gen2+
- M31 Once Again Ranked Among Forbes' "Asia 200 Best Under a Billion" List
- DeepComputing and Andes Technology Partner to Develop the World's First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop
Most Popular
- YorChip announces Low Latency 200G Chiplet for edge AI
- Alphawave Semi Q3 2024 Trading and Business Update
- RISC-V Announces Ratification of the RVA23 Profile Standard
- Arteris and SiFive Deliver Pre-verified Solution for the Datacenter Market
- MosChip Technologies joins Renesas RZ Partner Ecosystem as AI/ML Design Partner
E-mail This Article | Printer-Friendly Page |