With the MIPS® CorExtend™ Capability, VOCAL Achieves High-End DSP-Like Performance on an Industry-Standard Microprocessor
AMHERST, N.Y., January 27, 2003 – VOCAL Technologies, Ltd., a leading application developer of software and hardware for the communications industry, today announced that is has shown multiple flavors of xDSL baseband or 802.11 MAC functions can be subsumed into a new Pro Series microprocessor core from MIPS Technologies (see companion press release dated January 27, 2003 from MIPS Technologies). This capability enables value-enhanced multi-protocol consumer communication SOCs, with smaller die size than what can be achieved with a traditional DSP implementation.
The Pro Series family of cores from MIPS Technologies features the CorExtend capability that enables designers to supercharge their design's performance by adding application-specific knowledge and instructions to a 32-bit core MIPS core. This capability is unique among industry-standard architectures and underscores the power and ability of a general purpose microprocessor to subsume the hardwired logic of an SOC. In turn, engineers can reduce total design costs by reducing silicon area and design time.
"The use of MIPS Technologies' new CorExtend capability provides a very powerful mechanism to extend the performance of an industry-standard architecture in ways that eliminate part of the design effort of DSP-intensive designs," said Dr. Victor Demjanenko, CTO of VOCAL Technologies. "Now, MIPS licensees can replace DSP functionality all together by leveraging the work our engineers have done and exploiting the parallelism in the MIPS architecture. Ultimately, we expect broad adoption of this technology."
"VOCAL has given SOC designers a proven pathway to stay ahead of the rapidly changing communications standards with products that leverage and extend the functionality of an industry-standard processor," said Brad Holtzinger, director of systems solutions for MIPS Technologies. "The MIPS core, with its efficient RISC instruction set and optimized C compilers, used native instructions and the CorExtend capability to perform the signal processing functions. The result is lower SOC die size and streamlined SOC programming models."
Benchmark Results from VOCAL Technologies
The comparison table below illustrates benchmarks which are representative of the performance possible using a 32-bit Pro Series core from MIPS Technologies and VOCAL Technologies optimized algorithms and specific implementations:
| Optimized Software (No Pro Instructions) || VOCAL Software and Pro || TI C62x DSP || TI C64x DSP |
|Reed Solomon Encode Syndrome |
|8237 cycles per block ||1184 cycles per block ||-- ||-- |
Reed Solomon Decode Syndrome
|37,089 cycles per block ||421 cycles per block ||1680 cycles per block ||460 cycles |
| AES Encrypt |
|774 cycles per block |
|64 cycles per block |
|227 cycles per block |
|837 cycles per block |
64 cycles per block
|268 cycles per block |
|FFT Radix 2 |
|34,560 cycles per |
|3,583 cycles per |
|9,416 cycles per |
| 4,500 est. |