NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
3-D Stacking Reaches New Heights : Tachyon Semiconductor Creates Four-Wafer Stack
Naperville, IL - February 7, 2003 - The semiconductor industry has reached a new milestone with the creation of a 3-D silicon structure built of four silicon wafers. Tachyon Semiconductor Corporation, which created the four-wafer stack in August of 2002, believes it to be the very first multi-wafer stack ever achieved. Previous stacking announcements (by Tachyon and others) have described the bonding of only two silicon wafers.
Wafer stacking is of great interest to semiconductor manufacturers, who hope to build fast, dense multi-layer devices by using wafer stacks. In addition to speed and density, 3-D silicon devices promise lower power consumption and higher optimization than 2-D chips.
The ground-breaking four-wafer stack was created to test stress management parameters, the integrity of multiple interfaces, the results of ultra-thinning, and the mechanical dicing process that will cut wafer stacks into stacked chips. Variable bonding surfaces were incorporated in order to investigate several engineering issues, and voids were deliberately introduced to test a non-destructive void detection and calibration technique. The results of the tests, Tachyon says, amply confirmed the viability of their stacking process and demonstrated the potential to incorporate virtually any number of layers.
Tachyon's unique stacking process uses copper-to-copper thermal diffusion to bond standard silicon wafers without introducing any adhesives or dielectric materials. After the first two wafers are bonded, the top wafer is thinned to 5 microns; additional wafers are bonded and thinned in turn. The extreme thinning facilitates through-wafer electrical connections and heat dissipation; it also ensures that future multi-layer devices will fit into standard packaging.
Tachyon Semiconductor Corporation is a privately held fabless semiconductor and engineering design services company that has developed significant intellectual property concerning stacked memory and stacked SOC (System-On-a-Chip) integrated circuits. To learn more about Tachyon's technology, visit www.tachyonsemi.com on the World Wide Web.
# # #
|
Related News
- Broadcom acquires Stellar Semiconductor to expand 3-D offerings
- First 3-D processor runs at 1.4 Ghz on new architecture
- Xilinx Demonstrates Industry's First Scalable 3-D Graphics Hardware Accelerator for Automotive Applications
- Xilinx And Pixel Velocity Team To Deliver World's Most Advanced 3-D Recognition Technology
- Renesas Technology Releases "OpenGL ES Library" 3-D Graphics Software for SH-Mobile3 Application Processor
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |