eInfochips provides SOC engineering services to Astera Labs in developing industry's first PCIe 4.0 & 5.0 Smart Retimer SoC.
The Physical Implementation services from eInfochips made possible a first-pass success for Aries PCIe® 4.0 & 5.0 Smart Retimer SoCs.
San Jose -- August 17, 2020 -- eInfochips, a leading provider of product engineering and semiconductor design services, worked with Astera Labs to develop their portfolio of Aries Smart Retimers for PCIe® 4.0 and 5.0 technologies. Astera Labs is the preeminent enterprise working on Smart Retimer SoCs for PCIe 4.0 and 5.0 applications with up to 32 bi-directional lanes and plug-and-play interoperation at 32 GT/s speeds (on PCIe 5.0 technology). The eInfochips team provided services for the physical implementation and DFT architecture of the chip to make the Aries Smart Retimer production-ready.
Operating exclusively in the cloud for product development, Astera Labs is one of the first to develop complex SoCs entirely on the cloud and achieve a high degree of operational flexibility.
eInfochips offers end-to-end semiconductor design, verification and physical design services. eInfochips specializes in lower geometry designs and has taped-out 200-plus chips from 180nm to 7nm for diverse applications.
“This not only marks an important milestone in our proud relationship with Astera labs, but also reaffirms our belief in our engineers,” said Saurabh Desai, vice president and general manager of the ASIC business unit, eInfochips. “Our 25-plus years of experience in the silicon design to verification value chain ensures that we deliver world-class output, and thereby accelerate time to market for our clients.”
“eInfochips is an integral partner complementing our core competencies in developing purpose-built connectivity solutions with their expertise in silicon design. The diligence, commitment and expertise of the eInfochips team ensured that the design was a first pass success,” said Sanjay Gajendra, chief business officer at Astera Labs. “We look forward to continuing our association as we expand our product portfolio."
About Astera Labs
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards and services to enable robust PCIe connectivity. Partnering with leading processor vendors, cloud service providers, seasoned investors and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in compute-intensive workloads. For more information about Astera Labs, see www.AsteraLabs.com.
About eInfochips
With 25-plus years of experience in the semiconductor industry, eInfochips has expertise in developing Verification IPs, custom ASICs, SoCs, and FPGAs, and has strong knowledge of Ethernet, PCI Express, CXL, HBM, LPDDR5, NVMe, eMMC, and USB protocols to name a few. With 200-plus tape-outs, eInfochips has expertise in dealing with digital and mixed signal SoCs. eInfochips works with six of the top 10 semiconductor companies and has been recognized as a leader in semiconductor design services by many top analysts and industry bodies, including Gartner, Zinnov, Nasscom and others.
For more information visit www.einfochips.com
|
Related News
- Synopsys Design and Verification Solutions Enable Astera Labs to Develop Industry's First PCIe 5.0 Retimer SoC
- Astera Labs Verifies Its System-Aware PCI Express 5.0 Smart Retimer Using Avery Design Systems PCIe 5.0 Verification IP
- PCIe 5.0 & PCIe 4.0 PHYs and Controller IP Cores are available for immediate licensing to maximize your Interface speed for complex SoCs
- PCIe 4.0 Heads to Fab, 5.0 to Lab
- Astera Labs and Avery Design Partner on CXL 2.0 Verification for Smart Retimer Portfolio to Improve Performance in Data-Centric Applications
Breaking News
- Fractile raises $15m seed funding to develop radical new AI chip and unlock exponential performance improvements from frontier AI models
- Ceva Bluetooth Low Energy and 802.15.4 IPs Bring Ultra-Low Power Wireless Connectivity to Alif Semiconductor's Balletto Family of MCUs
- Agile Analog delivers customizable IP on GlobalFoundries' FinFet and FDX processes
- Ian Walsh appointed as Sondrel's Regional VP for America
- Systems Designed Today Must Support Post-Quantum Cryptography Tomorrow
Most Popular
- Imagination Technologies announces new capital investment from Fortress Investment Group
- Alphawave Semi: Q2 2024 Trading and Business Update
- Agile Analog delivers customizable IP on GlobalFoundries' FinFet and FDX processes
- Efinix Releases Topaz Line of FPGAs, Delivering High Performance and Low Power to Mass Market Applications
- Comcores supports BAE systems as a key partner with JESD204C IP
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |