Gain Technology Unveils Silicon-Verified USB 2.0 PHY Transceiver Core
INTEL DEVELOPER FORUM, SAN JOSE, Calif., August 27, 2001 - Gain Technology announced today that its GT3100 USB 2.0 Physical Layer (PHY) transceiver intellectual property (IP) core has received certification from the USB Implementers Forum. This "Hi-Speed" compliance milestone ensures GT3100 users of complete interoperability with emerging next-generation USB 2.0 enabled PCs and peripherals. USB 2.0's plug-and-play interface coupled with its 480-Mbps transfer rate provides a significant performance boost to peripherals such as optical scanners, portable storage, external CD-R/W, desktop and hand-held video cameras, and inkjet and laser printers.
"We are very pleased that our USB 2.0 PHY core has passed USB 2.0 compliance testing from the USB-IF," said Roy Kaller, Vice President of Engineering at Gain Technology. "With USB-IF certification, our customers will have added confidence that their system-on-chip (SoC) designs utilizing the GT3100 will meet the rigorous interoperability standards established by the industry." In addition to compliance to the USB 2.0 industry specification, the GT3100 core also complies with the USB 2.0 Transceiver Macrocell Interface (UTMI) standard.
"The availability of certified Hi-Speed USB 2.0 IP from Gain Technology will help enable SoC designers to meet aggressive time-to-market targets," said Jason Ziller, Intel technology initiatives manager and USB-IF chairman. "USB Implementers Forum certification of USB 2.0 building block products such as Gain's GT3100 will help speed deployment of next-generation, high-bandwidth PC peripherals."
Power and Area Efficient
At 165mW absolute maximum power dissipation, the GT3100 provides best-in-class power dissipation and is the only solution currently available to design low-power bus-powered functions that must operate within the 100mA limit imposed by the USB 2.0 specification. The GT3100 draws a maximum of 65mA in High Speed mode, leaving the designer 35mA to power other circuitry. The GT3100's die area of 1mm2 is believed to be the industry's most area efficient USB 2.0 PHY core implementation and helps SoC designers deliver low cost, highly integrated solutions.
Available as a licensed core, the GT3100 is initially fabricated on TSMC's 0.18-micron CMOS digital logic process. Silicon samples of the GT3100 and supporting documentation are immediately available. Visit www.gain.com for more support information.
About USB 2.0
Universal Serial Bus (USB) enables cost-effective, outside-the-box connectivity with plug-and-play capability for personal computer, consumer, industrial, embedded computing and PC peripheral products. The current USB 1.1 standard is widely deployed in hundreds of millions of personal computers and peripherals including printers, scanners, keyboards, and digital cameras. USB 2.0 is a new backward compatible version of the specification designed to increase performance to 480-Mbps as compared to the existing transfer rate of 12-Mbps. More information can be found at www.usb.org.
About Gain Technology
Gain Technology Corporation is a privately held fabless semiconductor company that designs, develops and supplies high performance analog and mixed-signal integrated circuits and semiconductor intellectual property (IP) cores to semiconductor and systems companies worldwide. Through partnerships with strategic customers, wafer foundries and other vendors, Gain offers its customers both product design services and complete product delivery of Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs) and semiconductor IP solutions. Gain is headquartered at 2700 West Broadway Blvd., Tucson, AZ 85745, Ph: (520) 628-9000, Fax: (520) 545-9214. Visit www.gain.com for more information.
Phil Davies, Director of Marketing and Sales
Gain Technology Corporation
Ph: (520) 628-9000 ext111
Fax: (520) 545-9214